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Posts Tagged ‘FinFETs’

FinFETs: Steptoe says bring ‘em on

Thursday, August 15th, 2013


Kevin Steptoe is VP of Engineering at Sondrel, a global chip-design consultancy based in Reading, U.K. We spoke this morning by phone about the future of FinFETs, in particular Steptoe’s reaction to my blog posted earlier this month, FinFETs: Yes, No, Maybe.

Steptoe said there’s nothing maybe about FinFETs. They are most definitely “an absolute yes” – revolutionary and disruptive as they may be – and offer great promise for the future of chip design, manufacturing, and deployment. And he said, his enthusiasm for the technology is not just from Sondrel’s point of view, but from his own personal involvement in the industry that extends back several decades.

Per Steptoe: “As the world’s increasingly insatiable demand for mobile, tablet-based, higher frequency devices ramps up, the predominant challenges for engineers and designers translate into fears of leakage power and performance. The FinFET, in its construction, addresses these challenges and makes mobile devices dramatically more possible.

“[In fact], the control of the short-channel affect and suppression of leakage actually simplifies things, so engineers will have the opportunity to achieve much higher [transistor] density, much lower power, and similar-or-increased performance levels. We see FinFETs as a win all the way around, a no-brainer that will fully live up to what it says on the tin: With FinFETS you will design ever larger devices with an ever higher power profile.”


Vertigo: funFITs or fudFITs into finFETS?

Thursday, March 28th, 2013


To say this is the year of the finFET is somewhat of an understatement, because everywhere you go somebody’s talking about going up instead of out – at ISSCC, at DesignCon, at DVCon, at ISQED, at SNUG, at EDPS, at DAC.

Among the talks so far, one of the best was given by the father of the finFET himself, U.C. Berkeley’s Chenming Hu. If you were at ISQED in Santa Clara on March 5th, you heard Prof. Hu describe how increasing leakage current in planar devices motivated radical new thinking in the late 1990s: Instead of a classic source, drain, gate structure, take a thin film of high-quality silicon material, place gate-dielectric above and below it such that the silicon is never very far from the gate, and then turn the thing 90 degrees so that the source is out the back, the drain’s in front, and the gate material is vertical.


GSS: a spirited defense of FDSOI

Thursday, December 13th, 2012


When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.

Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.

We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”


S2C: FPGA Base prototyping- Download white paper

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