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 What Would Joe Do?

Posts Tagged ‘finFET’

Helic: Blending the Long View with Pragmatic Realities

Thursday, October 5th, 2017

 


Taking guidance from their website
, Silicon Valley based Helic provides “EDA software that mitigates the risk of electromagnetic crosstalk in high-speed and low-power SOC designs.”

The company’s products include VeloceRF, an inductive device compiler and modeling tool which provides DRC clean devices for geometries as low as 10 nanometers; RaptorX, a pre-LVS electromagnetic modeling tool; and Exalto, a post-LVS RLCk extraction tool that captures unknown crosstalk including electrical, magnetic, and substrate coupling.

In other words, Helic is a company with a very technical portfolio of products, which can be daunting if one wants to speak with the leadership.

But that was not the real problem posed during my recent conversation with Helic President and CEO Yorgos
Koutsoyannopoulos
. The last time the two of us spoke, he made a bet I could not pronounce his name correctly. I won that bet, although Koutsoyannopoulos then proceeded to pronounce my name correctly as well, something that fewer than 1-in-10 in EDA can actually do.

Alas during our recent conversation – the one documented below – the Helic CEO could still pronounce my last name correctly, but I stumbled over his.

In my defense, Koutsoyannopoulus has 16 letters, 56% of which are vowels, and I hadn’t practiced in advance of our call. My last name only has 8 letters, but 63% of them are vowels, so mine is actually more difficult to pronounce. I should not have let Yorgos best me in this contest. Next time I will be better prepared.

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Solido’s Recipe: Platform, Patents, Customers, Poise

Thursday, August 31st, 2017

 


Amit Gupta is the quintessential entrepreneur in EDA.
Even as he was graduating with degrees in EE and CS from University of Saskatchewan, he was co-founding Analog Design Automation, targeted at those who need tools to automate analog chip design. That was in 1999. The company was sold to Synopsys in 2004, and then Gupta co-founded Solido Design Automation in 2005.

This week, I had a chance to speak at length with Amit Gupta. The last time we conversed, it was at the January 2017 Kaufman Award dinner for Dr. Andres Strojwas in San Jose. That evening, Gupta was enthused about Solido’s access to high-quality engineering talent in Canada, and argued that the cost of living and quality of life in Saskatoon, where Solido is headquartered, more than compensate for any sense that Silicon Valley is the epicenter of the industry. His enthusiasm has only grown since that time.

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Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013

 

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

****************
Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

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FinFETs: Yes, No, Maybe

Thursday, July 25th, 2013

 

Ed Sperling, Editorial Director for Semiconductor Manufacturing and Design Community, moderated a breakfast panel on Tuesday morning, June 4th, at DAC. Having missed the bulk of the event, I was fortunate to have a chance later to review the slides of the five speakers:  Cavium Networks VP Anil Jain, GlobalFoundries VP Subramani Kengeri and Director Kelvin Low, and Synopsys VP Raymond Leung and Senior Director Bari Biswas.

Having now gone through the slide deck twice, I’ve come away with a set of conflicting messages. On the one hand, the challenges of FinFET implementation are so great there is still much to be done, and the promise of the technology is yet to be fully proven. On the other hand, the synergy between GlobalFoundries and Synopsys is so excellent the challenges associated with FinFET implementation are definitely being met. So which is the more accurate message?

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DAC 2013: carpe diem with Ten in Texas

Thursday, May 16th, 2013

 

Let’s be honest. If you haven’t booked your flight and hotel yet for the Design Automation Conference in Austin in the first week of June, you’ve probably decided you’re not going. If that’s the case, more’s the pity because the sessions alone are going to be great, above and beyond the parties and networking, and will make the trip totally worthwhile. Here’s a sampling of the some of the topics that will be among the most compelling, with an acknowledgment that not everybody’s interests are the same.

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CST: Webinar series



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