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Posts Tagged ‘eda2asic’

Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013


Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.


EDPS 2013: surf, sand, serenity, semiconductors

Thursday, April 4th, 2013


Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.


EDPS: 3D-IC Showers & Flowers

Friday, April 6th, 2012


It’s April 2012, and both spring and 3D-ICs are in the air. But if Spring means April showers and May flowers, what do 3D-ICs mean?

Well, if you were at EDPS in Seaside this morning, at the Monterey Beach Resort, you would have heard from a host of speakers all addressing the April showers and May flowers of 3D-ICs. The session was organized and well moderated by eda2asic’s Herb Reiter.

* Showers –

Heat … 3D-ICs kick up a lot of thermal issues between the layers.

* Flowers –

Multiple solutions are under consideration for heat. If you’re rich like IBM, you talk about micro-channels where cooling waters will flow. If you’re not rich – like everybody else – you don’t yet know what to do to sink that heat off-chip and out of harm’s way. Micro channels are too exotic, so stay tuned as solutions are sought out and implemented.

* Showers –

EDA Flow … it’s not quite here, according to many, even though the current tools may be good enough for some. Most believe there are larger needs that should be met.


S2C: FPGA Base prototyping- Download white paper

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