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Posts Tagged ‘DVCon’

Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment

Thursday, July 14th, 2016

 


Intel’s Shishpal Rawat has been Chair of Accellera for 6 years and is currently serving as President of CEDA
, IEEE’s Council on Electronic Design Automation. In previous discussions, Rawat has insisted that his leadership is not what makes these organizations work. Only the enthusiastic efforts of the many members guarantee that both Accellera and CEDA continue to shape ideas, standards, and forward progress within design automation and its adjacent technologies.

Two years ago, I enjoyed a lengthy interview with Rawat about all of this, described here. This year, I’ve chatted with Rawat at DVCon in San Jose in March, and again by phone just prior to DAC in June. During the phone call, Rawat focused on CEDA’s activities at DAC in Austin. He told me the upcoming Sunday night panel, set to be moderated by SRC’s Bill Joyner on June 5th, was a new and very exciting addition to the DAC program.

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Accellera’s PSWG: Realists and Optimists, the lot of them

Thursday, March 17th, 2016

 


Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon
several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

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Ajoy Bose: The Man Behind the Microchip

Thursday, March 10th, 2016

 


You would probably have learned more about Ajoy Bose
by reading his biography than by attending Jim Hogan’s gentle exercise in collegiality on Tuesday night, March 1st, in Silicon Valley. The conversation between these two giants of EDA, hosted by EDAC as part of DVCon week, was consistently unstructured, whimsical and seemingly without outline.

The next day, I sat in a coffee shop and struggled to find a handle with which to write a coherent summary of the previous night’s random access memory album. But that handle would not reveal itself.

Then I happened to glance over to a nearby table where another caffeine addict was buried in a book: The Man Behind the Microchip. I asked the addict who exactly was the subject of the book and the answer came back: Robert Noyce.

So Robert Noyce is the man behind the microchip, I pondered. The only man behind the microchip? Like Steve Jobs invented the iPod/iPad/iPhone? Or Thomas Edison invented the electric light?

No wonder, I realized, it was hard to get a handle on the previous night’s Hogan/Bose interview. They didn’t do anything. Robert Noyce did it all. And without help. Hogan and Bose did nothing, and ergo had nothing to offer their audience.

These two were not part of a vast conspiracy of contributors, all adding their particular drips and drops of innovation into the trickle of technology, that rolled into a small creek of creativity, that ran into a moderate-sized stream of science-turned-engineering, which poured into a roaring river of real change, which crashed into a seething sea of twenty-first century digital life.

Of course, that’s nonsense. Robert Noyce did not do everything, and Hogan and Bose did not do nothing.

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Attending DVCon: Read this first …

Wednesday, February 24th, 2016

 


Emulation is everything in verification today
and therefore at the center of DVCon. Technology expert, Lauro Rizzatti, has prepared this brief tutorial for you, so you’ll be ready for the conference that starts on February 29th.

* The Past

Hardware emulation has been around for 3 decades. It started in the mid 80s with pioneers like Quickturn and Ikos, who used off-the-shelf FPGAs in the fabric of their emulators. The second decade saw the rise of several startups, some of them using custom silicon devices in the emulators.

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DVCon Week: Bose and Hogan to Showcase Gravitas

Wednesday, February 10th, 2016

 


Sometimes you just gotta wonder
what happens behind the closed doors of the executive suite. Last June, when Synopsys acquired Atrenta, Atrenta’s founder – a distinguished technologist, alum of IIT Kanpur, UT Austin, Bell Labs, Cadence and Interra, and profoundly well-seasoned EDA leader – closed the door on his leadership role at the company he founded 14 years before.

I will admit, I do not know if Dr. Ajoy Bose actually ever reported to duty at Synopsys last summer – the received wisdom would have us believe he needed to set foot there long enough to help his team transition into the Big Purple – but in truth, it is hard to imagine him ever playing second fiddle to Dr. Aart de Geus or Dr. Chi-Foon Chan, or anyone else for that matter. He is a man of that much dignity and gravitas.

Of course, if Bose did punch a time clock at Synopsys, it was for nary a nanosecond in geologic time. It’s been 9 months since the acquisition and now Bose is clearly free to speak in public about the past, present and future of the industry he has helped to create. That surely would not be happening if Bose was just a node in the org chart that has Chan and de Geus at the top of the pyramid.

So there’s one half of the good news included herein.

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DVCon: The Imitation Game

Thursday, March 5th, 2015

 

What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall became even more animated.

What if I told you the technical portion of the conference included a variety of content — touching at times on autos, wearables, the IoT, IP, standards, and verification — excellent panel discussions, well-attended poster sessions, detailed tutorials, and a keynote from the CEO of the largest company in the industry delivered to a packed, SRO ballroom full of designers, engineers, and engineering managers.

Finally, what if I told you the highly capable staff of MP Associates was running the whole thing with their usual aplomb, attending to details as diverse as registration, sound systems, lunch tickets, speaker logistics, and awards presentations.

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Intel’s Shishpal Rawat: Multiple hats, Singular focus

Thursday, September 25th, 2014

 


Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat
, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.

Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.

He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”

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Fall Schedule: Let the games begin

Thursday, August 28th, 2014

 

With the advent of September, the fall conference season begins. Here are some upcoming meetings you may want to attend.

* DesignCon China – September 2-5 – Shenzhen
Last year close to 13,000 attended ICC-China. Expect even more to attend this year.

* Mentor Graphics Forum – September 3 & 5 – Shanghai & Beijing
Keynote will be given by Mentor CEO Dr. Wally Rhines, followed by President of ARM Greater China Allen Wu talking about the next 10 billion chips to be manufactured in China.

* IDF14: Intel Developers Forum – September 9-11 – San Francisco
Intel CEO Brain Krzanich will give opening keynote, followed by lots of talk about the IoT.

* PCB West 2014 – September 9-11 – Santa Clara
The most important conference of the year for board designers.

* Mentor U2U Automotive – September 10 – Dearborn
The debut of a new Mentor User2User event focusing on one of Mentor’s favorite core competencies.

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Agnisys: Automating spec checking

Tuesday, March 18th, 2014

 

Agnisys exhibited at DVCon several weeks ago in Silicon Valley, but within the time constraints of the show I didn’t have a chance to talk with them. Fortunately, that was remedied at 9 am this morning – 9:30 pm in Noida – during a phone call with company CEO Anupam Bakshi, who was visiting his team in India at the time of our conversation.

Prior to his involvement with Agnisys, Bakshi served at Avid Technology, PictureTel, Blackstone Consulting Group, Cadence, and Gateway Design Automation.

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WWJD – Let’s start with the elevator pitch. In 25 words or less, when did the company start and what do you do?

Bakshi – We started 6 or 7 years ago and are Massachusetts-based, although a lot of our development is done in Noida. Our products, called IDesignSpec, focus on the area that the big EDA companies don’t, providing an executable specification tool for chip design.

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CDNLive 2014: Delicious Sensory Overload

Wednesday, March 12th, 2014

 

In the spirit of full disclosure, Cadence paid for lunch yesterday for the Press Corps attending CDNLive 2014. We had a scrumptious gourmet meal at Tosca in the lobby of the Hyatt Regency before returning to the Santa Clara Convention Center next door to have an hour-long “one-on-one” with Cadence CEO Lip-Bu Tan. In truth, it was actually an hour-long “twenty-on-one” with CEO Tan, because all of the usual suspects EDA Press Corps was in the room throwing softball lobbing questions at Tan.

Over the course of the hour, we learned that CEO Tan has a host of different investment partners – sorry, didn’t write down the names – involved in his various VC-funded ventures that span everything from GoPro [the trendy wearable camera enterprise out of Half Moon Bay] to a fabless startup that he said can tape-out a design at 16 nanometers for a scant $15 million, rather than the usual $150 million being lamented today in the global press. [In fact, Tan mentioned so many ventures he’s involved with, it begs the question: How does he have time to run Cadence?]

We learned that CEO Tan is very excited about all of the technologies involved in the semiconductor design/supply chain, that he believes it’s a great time to be a player in the industry, and that Cadence is innovating rapidly on multiple fronts simultaneously. And if/whenever Tan senses that they’re slowing down in any particular area, he pushes Cadence Engineering to move forward even faster.

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