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Posts Tagged ‘Design rule checks’

Chattejee: Engineering reality trumps drama

Wednesday, March 21st, 2012

Because Pallab Chattejee went to upwards of 78 technical conferences last year, he probably knows a thing or two about the status of the industry today. It also helps that he’s a long-time IC design adviser, CTO of SiliconMap, a consultancy, and is ramping up a new online publishing presence, Media & Entertainment Technologies, with long-time tech guru Tets Maniwa.

Among his many involvements, including the IEEE Nanotech Council and U.C. Berkeley’s Engineering Alumni Society, Pallab has been associated with the International Symposium on Quality Electronic Design for all of its 13 years.

He’s headed up most of the committees at one point or another, and this year is serving for a second time as General Chair, so it’s not a complete surprise that Pallab has been named an ISQED 2012 Fellow.

What is a surprise, is Pallab’s candid assessment of the messages that are often the stuff of conference keynote speeches – even those given at ISQED – particularly when those speeches are offered up by EDA vendors or foundries. (more…)




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