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Posts Tagged ‘DATE’

Conferences: Paper submission deadlines approach

Thursday, July 28th, 2016

 


A number of conferences important to EDA and IP
 are coming up over the next 12 months and currently looking for content. If you have an industry-relevant topic you’d like to talk about, the organizers of some of these conferences need to hear from you soon. Various deadlines are looming, most over the next few weeks.

Meanwhile, it’s interesting to consider that one of the most thrill- for-your-buck conferences on the list is Black Hat USA 2016 and Synopsys’ co-located CodenomiCON, both promising to teach you everything you need to know or are allowed to know about cybersecurity. Synopsys’ involvement in Black Hat may validate a comment overheard recently: ‘Synopsys is no longer really an EDA company. They’ve become a software integrity company.’

Also interesting, DVCon in San Jose and Mobile World in Barcelona in 2017 are on the exact same days. Perhaps there’s no overlap in the attendee population. But most interesting on the list, the sheer scale of the China International Modern Industry & Intelligent Equipment Exhibition with 500+ exhibitors, over 40,000 attendees, and more topics that you can possibly imagine.

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Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment

Thursday, July 14th, 2016

 


Intel’s Shishpal Rawat has been Chair of Accellera for 6 years and is currently serving as President of CEDA
, IEEE’s Council on Electronic Design Automation. In previous discussions, Rawat has insisted that his leadership is not what makes these organizations work. Only the enthusiastic efforts of the many members guarantee that both Accellera and CEDA continue to shape ideas, standards, and forward progress within design automation and its adjacent technologies.

Two years ago, I enjoyed a lengthy interview with Rawat about all of this, described here. This year, I’ve chatted with Rawat at DVCon in San Jose in March, and again by phone just prior to DAC in June. During the phone call, Rawat focused on CEDA’s activities at DAC in Austin. He told me the upcoming Sunday night panel, set to be moderated by SRC’s Bill Joyner on June 5th, was a new and very exciting addition to the DAC program.

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Cadence Emulation: Schirrmeister articulates Both Sides of the Equation

Tuesday, April 7th, 2015

 

Frank Schirrmeister, Group Director of Product Marketing for the System and Software Realization Group at Cadence, had just returned from DATE in Grenoble when we spoke several weeks ago about the philosophy and technology behind Cadence’s emulation business unit. First, however, we spoke about Grenoble.

I asked Frank if DATE had been a success this year and he said, “Absolutely, yes. It was very interesting as it has transformed from a generic show into more of a technical conference. So the focus now is on the sessions.

“Particularly interesting for me, I was chair for a session about tools for the IoT. Jan Rabaay from U.C. Berkeley, always a good speaker, gave a great presentation on wearable trends. NXP also participated, talking about the connected car, and ARM spoke about their embed OS for the edge nodes. Also among those topics, we talked about debug. It was all very good.”

Having enjoyed DATE many times myself, I asked Frank what he thought distinguished the conference from DAC. He said, “First of all, DATE was in Grenoble, which is always a great destination. Then, of course, at DATE you see the European point for view.

“For instance, I had a presentation for my session regarding automotive issues, and included material of interest to our customers in Japan and Europe. The share of semiconductors in cars from those markets focuses more on the mission-critical pieces in the design. The focus is different for automotive customers in North America, where it centers more on mobile connectivity within the vehicle.”

All of this being very interesting, I turned the conversation to the real reason for our phone call: To allow Frank to clarify emulation at Cadence.

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2014: Conference Calendar Update

Thursday, January 9th, 2014

 

The New Year has arrived and with it a chance to reset the calendar for 2014. Following are only some of the conferences on the horizon. It’s interesting to look closely at the list to see which conferences are in direct scheduling conflict with each other.


* ASP-DAC 2014

Asia & South Pacific Design Automation Conference
Singapore – January 20-23

* DesignCon 2014

“Where the Chip Meets the Board”
Santa Clara – January 28-31

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EDAC CEO Panel: Practically perfection

Thursday, March 14th, 2013

 

From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.

Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.

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Blue Pearl: Facilitating FPGA design

Thursday, December 6th, 2012

 

Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.

Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.

“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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