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Posts Tagged ‘DAC’

MIT: towards the 1000-core processor

Tuesday, July 17th, 2012

 

MIT is a disorienting place, particularly Stata Center, the home of EECS. There are no straight lines in the building and nothing appears plumb. Architect Frank Gehry, it seems, wanted his design to disturb and overwhelm and there he has succeeded, particularly when it rains: The building leaks. But does the building also stimulate? Again, Gehry has succeeded: The building hums with energy.

On a sunny day in July, the place is crawling with people. Students of various ages, genders, and nationalities wander by chatting in their t-shirts and flip flops, professors share bag lunches with their children in shady corners of the labyrinthine lobby, the line at the deli counter queues around in a disorderly sort of meander, while people in suits mingle with the flip-flop crowd in and under staircases that wander up and off into brick-lined oblivion.

Stata is part intellectual Grand Central Station and part Winchester Mystery House, enticing tourists and visiting scholars alike to wander in off the ponderous corporate streets of Cambridge.

EECS Professor Srini Devadas has an office on the 8th floor of Stata. When we sat down to chat there on Monday, July 9th, he started with an enthusiastic endorsement of MIT’s most famous building.

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BDA: Two different definitions at DAC

Tuesday, July 10th, 2012

 

It’s stranger than fiction, but there are actually two different entities at DAC that bear the name BDA, and they’re both acronyms.

One is a company very familiar to the EDA space, Berkeley Design Automation. As you know, President & CEO Ravi Subramanian has just been elected to a second term as a member of the Board of Directors of EDAC.

Subramanian’s BDA is in the news again this week because they just announced that ATopTech, also an EDA company, is now using BDA’s Analog FastSpice to “enhance the accuracy of the timing analysis in [ATopTech’s] Aprisa P&R product for designs at advanced process technology nodes such as 28nm and 20nm..”

So what is the other BDA at DAC? It’s Biological Design Automation. The International Workshop on Biological Design Automation figured large on Sunday and Monday, June 3rd and 4th, in San Francisco where it was again co-located with the Design Automation Conference, as it has been for several years.

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SWVP: Gary Smith’s Four Horsemen of the Approximation

Thursday, June 14th, 2012

 

Everybody loves the phrase, Four Horsemen of the Apocalypse, but usually don’t remember the specifics. According to Wikipedia, the horsemen each ride a steed of a different color – white, red, black, and pale – and thunder towards us bearing apocalyptic messages of Conquest, War, Famine and Death. You know: The stuff of video games and CGI blockbusters. Ignore them and you lose.

This year at DAC, GSEDA analyst Gary Smith presented his own apocalyptic message in back-to-back presentations on Sunday evening, June 3rd, and again on Monday morning, June 4th.

Why was Smith’s message apocalyptic? Because he too had four horsemen, and they too cannot be ignored. Without them, products will fail. It’s that simple.

Smith’s horsemen are neither rapacious nor ravaging, however. Instead, they represent the methodical four-step process for co-development of hardware and software, which if done properly moves to completion in carefully controlled lock-step and produces successful results.

Replacing Apocalypse with Approximation, Gary Smith’s Four Horsemen of the Approximation represent Design Exploration (not Conquest), Making Apps (not War), Firmware (not Famine), and Sales & Marketing (not Death).

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49DAC Unplugged: Bob, Chris, Ry, Steve, Jennifer, Wally, Jill, Lee

Monday, June 4th, 2012

 

DAC started with a boom on Sunday night, June 3rd. EDAC reports that 900 people registered for the opening reception, and by the crush of people in Salon 7 in the basement of the San Francisco Marriott Hotel, it looked like everybody showed up. [Although perhaps not quite 900…]

Setting up my word processor on a cocktail table at the back of the crowd, I manged to see numerous thought leaders in EDA as they swam by, in and out of the stream of people that swirled throughout the wine, buzz & music-laden ballroom as EDAC’s Executive Director Bob Gardner’s Jazz Trio entertained up on stage.

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Dr. Belle Wei: 2012 Marie R. Pistilli Achievement Award

Thursday, May 24th, 2012

 

At the center of the technical universe sits Silicon Valley. At the center of Silicon Valley sits the City of San Jose. At the center of the city sits San Jose State University, and at the center of the university sits the Charles W. Davidson College of Engineering.

Currently, SJSU offers 12 undergraduate majors in engineering, 11 graduate majors, and a host of different inter-disciplinary programs at all levels. It’s a dynamic College of Engineering and a powerful magnet for study in Northern California.

Dr. Belle Wei (M.S.E. Harvard, Ph.D. U.C. Berkeley) has been Dean of the College of Engineering since 2002, and is now serving a second 6-year term. On Monday, June 4th, at the Design Automation Conference in San Francisco, Dean Wei will receive the 2012 Marie R. Pistilli Achievement Award.

Per the press announcement of her Marie R. Pistilli award: “Dr. Wei is the first person in the College of  Engineering’s history to hold an endowed deanship. During her tenure as dean, Dr. Wei has increased extramural grants and endowment gifts, strengthened industry partnerships, and tripled corporate master’s degree programs from five to 14.”

Dr. Wei – first interviewed here on EDACafe in 2006 – has a long, distinguished career at SJSU. Her contributions to engineering education, in particular, the promotion of under-served populations who seek careers in technology, are extremely significant.

It was an honor to speak with Dean Wei this week about engineering education, innovation, and everything in between. We spoke on May 22, 2012.

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DAC 2012: Wicked Wednesday in San Francisco

Sunday, May 13th, 2012

 

DAC looms!

If you do nothing else on Wednesday, June 6th, at the Design Automation Conference be sure to attend the second of the two keynotes.

Intel’s Brad Heaney will be talking about “designing a 22nm Intel Architecture Multi-CPU and CPU.” It’s got well over a billion transistors and would have only been the stuff of Sci-Fi dreams a brief 15 or 20 years ago.

After that, just like on Terrible Tuesday, you’ve got a wicked wheelbarrow full of different ways you could go, starting with the User Track. The Wednesday line-up in this well-received recent addition to the DAC schedule includes:

* Packaging & Automatic P&R, with speakers from Mentor Graphics, Samsung, and Intel
* Keynoter Q&A, with the morning’s IBM & Intel speakers fielding questions from the crowd
* Practical Formal Methods, with speakers from IBM, Oski, and Intel

If your interests, however, reside with the young more than the mega-organizations in the EDA ecosystem, Wednesday is your day to visit the ACM Sigda University Booth in the Exhibition Hall, where the “new EDA tools, EDA tools applications, design projects, and instructional materials” will be your guide to the future minds of this industry.

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DAC 2012: Terrible Tuesday in San Francisco

Tuesday, May 8th, 2012

 

DAC looms!

And never more so than on Tuesday — especially this year, June 5th, when you’re going to have to make some terrible decisions about what to miss, and what not to miss.

First there’s the opening session in the morning when a boatload of awards are handed out, followed by the 2012 keynote. The Exhibition Hall won’t open until these things wrap up, so other than company meetings or company special-product announcement breakfasts, you should be able to be in the main theater at Moscone from 8:30 to 10:00 am or so.

Of course, worst case scenario: The opening session at DAC is always video-taped, so you could watch it at a later date after it’s uploaded to the DAC website but that’s hardly ideal.

This year’s main address will be delivered by ARM’s Mike Muller, “comparing the original ARM design of 1985 to those of today’s latest microprocessors … how far design has come and what EDA has contributed to enabling … systems, hardware, operating systems, and applications.” Then Muller plans to talk about 2020, how to get there, and what it will be like when we do. Conclusion? This stuff’s better heard in person than tape delayed. Go to the opening session, and plan not to regret it.

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DAC 2012: Marvelous Monday in San Francsico

Monday, May 7th, 2012

 

DAC looms!

It’s time to start examining the Conference Program and figure out how you’re going to spend your time in the first week of June when you’re attending the Design Automation Conference next month in San Francisco at Moscone Center.

Marvelous Monday …

On Monday June 4th at DAC there’s so much going on you really need to take some time to seriously consider how you’re going to schedule your day. So, first click here to see the jam-packed program, and then figure out what your priorities are.

Sessions or Exhibition Hall? You better work on this now, because if you suffer from sensory overload syndrome, you’ll never figure it out on the day of.

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DAC 2012: Super Sunday in San Francisco

Sunday, May 6th, 2012

 

DAC Looms!

It’s time to start examining the Conference Program and figure out how you’re going to spend your time in the first week of June when you’re attending the Design Automation Conference next month in San Francisco at Moscone Center.

Super Sunday …

Sunday is never a Day of Rest for DAC attendees, and Sunday June 3, 2012 is no exception. First, there are 4 co-located conferences happening in Moscone Center on DAC Sunday:

* IWLS: International Workshop on Logic Synthesis
* SLIP: System Level Interconnect Prediction Workshop
* HOST: IEEE Internt’l Symposium on Hardware & Trust
* ESLsyn: Electronic System Level Synthesis Conference

There are also 7 DAC-related workshops:

* CMOS Design at 60 GHz & Beyond
* Moore than More Technologies
* EDA & Process Automation
* Bio-Design Automation
* Young Faculty at DAC
* System-level Design of Automotive Electronics & Software
* Computing in Heterogeneous, Autonomous ‘N’ Goal-oriented Environments

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Chattejee: Engineering reality trumps drama

Wednesday, March 21st, 2012

Because Pallab Chattejee went to upwards of 78 technical conferences last year, he probably knows a thing or two about the status of the industry today. It also helps that he’s a long-time IC design adviser, CTO of SiliconMap, a consultancy, and is ramping up a new online publishing presence, Media & Entertainment Technologies, with long-time tech guru Tets Maniwa.

Among his many involvements, including the IEEE Nanotech Council and U.C. Berkeley’s Engineering Alumni Society, Pallab has been associated with the International Symposium on Quality Electronic Design for all of its 13 years.

He’s headed up most of the committees at one point or another, and this year is serving for a second time as General Chair, so it’s not a complete surprise that Pallab has been named an ISQED 2012 Fellow.

What is a surprise, is Pallab’s candid assessment of the messages that are often the stuff of conference keynote speeches – even those given at ISQED – particularly when those speeches are offered up by EDA vendors or foundries. (more…)

CST: Webinar series



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