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Posts Tagged ‘Cliff Hou’

Herb Reiter at EDPS: Multi-Die IC Design and Application

Thursday, March 24th, 2016


To speak with Herb Reiter about the rationale for multi-die packaging
is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.

Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.


Vertigo: funFITs or fudFITs into finFETS?

Thursday, March 28th, 2013


To say this is the year of the finFET is somewhat of an understatement, because everywhere you go somebody’s talking about going up instead of out – at ISSCC, at DesignCon, at DVCon, at ISQED, at SNUG, at EDPS, at DAC.

Among the talks so far, one of the best was given by the father of the finFET himself, U.C. Berkeley’s Chenming Hu. If you were at ISQED in Santa Clara on March 5th, you heard Prof. Hu describe how increasing leakage current in planar devices motivated radical new thinking in the late 1990s: Instead of a classic source, drain, gate structure, take a thin film of high-quality silicon material, place gate-dielectric above and below it such that the silicon is never very far from the gate, and then turn the thing 90 degrees so that the source is out the back, the drain’s in front, and the gate material is vertical.


S2C: FPGA Base prototyping- Download white paper

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