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 What Would Joe Do?

Posts Tagged ‘Cadence’

Paul Estrada: BDA with an ACE up its sleeve

Thursday, May 23rd, 2013

 

BDA chief operating office Paul Estrada has been at Berkeley Design Automation for over 7 years and is as enthused about the company today as when he first arrived. Particularly, because he says BDA is getting more attention than ever these days thanks to its growing portfolio of leading-edge products.

“We are a small business that continues to grow,” Estrada says with pride, “focusing on nanometer verification, a market where there are lots of problems, but where we are definitely making [inroads]. It’s an area that’s ripe for innovation, and better tooling, and as we don’t see the big EDA companies putting time or effort into making progress there, it’s a sweet spot in the market for us.”

Sounds great, so what’s the elevator pitch for potential customers?

Estrada responds easily: “Many companies continue to buy from our competition – principally Cadence and Synopsys – but we go into leading edge RF and analog/mixed-signal design teams and ask them what they can’t do with their current tools. They tell us and then we do those things for them with our tools. As a result, they buy even more tools from us and we go on from there.

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Sanjiv Kaul: Calypto and HLS to seize the day

Thursday, May 16th, 2013

 

Privately-held Calypto is on quite a clip these days, with developments at the company being closely followed by the press. That’s not completely surprising given that a new CEO came on board earlier this year, Sanjiv Kaul, and a new VP of Applications Engineering was named just this week, Thomas Bollaert being promoted into that role. I had a chance to speak with CEO Kaul recently. Following is a snapshot of that conversation.

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Cicero to Costello: Know your audience, breathlessly

Wednesday, May 1st, 2013

 

Joe Costello came to town tonight and wowed his acolytes.

Thanks to EDAC, Kathryn Kranen, Steve Pollock, Bob Gardner, Jennifer Cermak, Jill Jacobs, Gloria Nichols, and CadenceJim Hogan hosted Costello on stage at Cadence’s San Jose Headquarters for a 90-minute event that was one part Reunion Tour [lotsa Cadence alums in the audience in addition to the two on stage], one part Pity Party for Mentor Joe & Mentor Jim [oh so many visits to VCs who failed to embrace a startup’s pitch], and one part Brag Fest for VC Joe & VC Jim [oh so many visits from potential startups whose pitch we simply could not embrace].

Add up those parts and you’ve still only got half of the content of tonight’s event; the other half of the Joe Costello Love-in consisted of a detailed Lesson in Rhetoric. Perhaps not surprising, given that the event was titled: Joe Costello Shares His Secrets for Communicating a Compelling Company Story. What is surprising is how closely Costello’s advice to his adoring audience mirrored Cicero’s Five Canons of Rhetoric.

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EDPS 2013: surf, sand, serenity, semiconductors

Thursday, April 4th, 2013

 

Let’s be honest about this. The reason the Electronic Design Process Symposium takes place every year in Monterey is because of the surf and sunshine. Otherwise, this conference would be so much more appropriately located in Silicon Valley.

Oh well, where’s the harm? Just hop into your favorite woodie, be it a hybrid or an EV, don’t forget the suncream, sandtoys, and surfboard, and head on down to Monterey Bay for two days of great talks, good food, and quiet-ish contemplation, with an emphasis on -ish. The 20th annual EDPS awaits.

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DAC 2013: Innovation Square

Thursday, March 21st, 2013

 

It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.

Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.

In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.

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EDAC CEO Panel: Practically perfection

Thursday, March 14th, 2013

 

From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.

Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.

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DVCon 2013: Best Practices in Verification Planning

Thursday, February 28th, 2013

 

Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”

Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.

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DVCon 2013: There is such a thing as a free lunch!

Thursday, February 21st, 2013

 

You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.

If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.

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Ausdia: Sanjay Lall joins the board

Thursday, November 8th, 2012

 

It might be the impression of late that all EDA-startup roads lead to Synopsys, but that would be incorrect. Small, privately-held companies continue to make their way in the industry, independent and productive.

Ausdia, based in Silicon Valley, has been underway since 2006 developing tools for timing constraint verification and management. Today the company announced a new board member, Sanjay Lall. Per the press release, Lall has 20+ years of experience in the EDA and semiconductors, “an expert in operations, marketing, fund raising and sales.”

He is also Chairman and Managing Partner at Cronox Group, on the Board of Advisors at Verdigirs Technologies, and a Director at Mobi-holdings. Previously, Lall was VP of Sales at Extreme DA, and “influential in the company’s acquisition by Synopsys in 2011.”

All EDA-startup roads may not lead to Synopsys, but not surprisingly the CVs of most seasoned EDA veterans do lead to Synopsys, and/or to Cadence and/or Mentor Graphics.

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ProPlus: DFY solution unveiled

Thursday, November 1st, 2012

 

The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.

In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.

Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.

“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.

“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”

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