Posts Tagged ‘Cadence’
Thursday, April 21st, 2016
Just as Auguste Rodin revived the art of sculpture at the end of the 19th century in Europe, and Wynton Marsalis rescued the art of jazz by the end of the 20th century in America, here in the 21st century University of Illinois CS professor Rob Rutenbar is resurrecting the art of teaching VLSI design around the world.
He’s doing that via his Coursera-based online class entitled VLSI CAD: Logic to Layout, a course with an enrollment that defies comprehension. Per Rutenbar’s own whimsy: “There are about 25,000 people working in the EDA industry today. About 55,000 of them have signed up for my class.”
I had a chance to speak by phone with Dr. Rutenbar earlier this week. He was sitting in his office in Urbana-Champaign, but looking out an academic landscape that encompasses the entire world.
[hint: a MOOC is a Massively Open Online Course.]
Thursday, March 17th, 2016
Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.
After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.
I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?
Thursday, March 10th, 2016
You would probably have learned more about Ajoy Bose by reading his biography than by attending Jim Hogan’s gentle exercise in collegiality on Tuesday night, March 1st, in Silicon Valley. The conversation between these two giants of EDA, hosted by EDAC as part of DVCon week, was consistently unstructured, whimsical and seemingly without outline.
The next day, I sat in a coffee shop and struggled to find a handle with which to write a coherent summary of the previous night’s random access memory album. But that handle would not reveal itself.
Then I happened to glance over to a nearby table where another caffeine addict was buried in a book: The Man Behind the Microchip. I asked the addict who exactly was the subject of the book and the answer came back: Robert Noyce.
So Robert Noyce is the man behind the microchip, I pondered. The only man behind the microchip? Like Steve Jobs invented the iPod/iPad/iPhone? Or Thomas Edison invented the electric light?
No wonder, I realized, it was hard to get a handle on the previous night’s Hogan/Bose interview. They didn’t do anything. Robert Noyce did it all. And without help. Hogan and Bose did nothing, and ergo had nothing to offer their audience.
These two were not part of a vast conspiracy of contributors, all adding their particular drips and drops of innovation into the trickle of technology, that rolled into a small creek of creativity, that ran into a moderate-sized stream of science-turned-engineering, which poured into a roaring river of real change, which crashed into a seething sea of twenty-first century digital life.
Of course, that’s nonsense. Robert Noyce did not do everything, and Hogan and Bose did not do nothing.
Wednesday, February 24th, 2016
Emulation is everything in verification today and therefore at the center of DVCon. Technology expert, Lauro Rizzatti, has prepared this brief tutorial for you, so you’ll be ready for the conference that starts on February 29th.
* The Past
Hardware emulation has been around for 3 decades. It started in the mid 80s with pioneers like Quickturn and Ikos, who used off-the-shelf FPGAs in the fabric of their emulators. The second decade saw the rise of several startups, some of them using custom silicon devices in the emulators.
Wednesday, February 10th, 2016
Sometimes you just gotta wonder what happens behind the closed doors of the executive suite. Last June, when Synopsys acquired Atrenta, Atrenta’s founder – a distinguished technologist, alum of IIT Kanpur, UT Austin, Bell Labs, Cadence and Interra, and profoundly well-seasoned EDA leader – closed the door on his leadership role at the company he founded 14 years before.
I will admit, I do not know if Dr. Ajoy Bose actually ever reported to duty at Synopsys last summer – the received wisdom would have us believe he needed to set foot there long enough to help his team transition into the Big Purple – but in truth, it is hard to imagine him ever playing second fiddle to Dr. Aart de Geus or Dr. Chi-Foon Chan, or anyone else for that matter. He is a man of that much dignity and gravitas.
Of course, if Bose did punch a time clock at Synopsys, it was for nary a nanosecond in geologic time. It’s been 9 months since the acquisition and now Bose is clearly free to speak in public about the past, present and future of the industry he has helped to create. That surely would not be happening if Bose was just a node in the org chart that has Chan and de Geus at the top of the pyramid.
So there’s one half of the good news included herein.
Wednesday, January 20th, 2016
Just short of 2 years ago, the EDA press corps sat in a room in the Hyatt Regency in Santa Clara and enjoyed a face-to-face with Cadence CEO Lip-Bu Tan. A full report of that conversation is available here, but it is the closing segment of the report that informs this blog:
Finally, the Cadence PR machine closed out the hour by making sure the Press Corps was privy to the human side of CEO Tan. It would appear his wife does not make the tech-product purchasing decisions at home as much as do the two boys. Tan said that his two CMU-educated engineer sons are smart and savvy, and had advised him early on to invest in both Netflix and Tesla. Tan humbly acknowledged that he had, unfortunately, ignored those two pieces of advice and hence had lost out on the opportunity to win big in both movies and EVs.
So, here’s the hypothetical: Given Lip-Bu Tan’s involvement with a $2 billion investment group – efforts interleaved with his responsibilities as Cadence CEO – wouldn’t it have been wise to harvest stock tips from his press meeting back in March 2014 in Santa Clara?
Thursday, January 7th, 2016
If you’re interested in the past, the third quarter of 2015 is a good place to start: the EDA/IP industries did very well from July through September last year. EDAC’s Market Statistics Service numbers, released this week, offer some of the details. Here’s the link if you want to delve in.
Easier however, is this brief summary of my January 5th phone call with Mentor’s perpetually optimistic CEO Wally Rhines, last year’s EDAC/CEDA Kaufman Award winner and this year’s EDAC spokesman [technically, every year’s].
Although there was snow and ice on the roads around Wilsonville, Oregon, when we talked, nothing could put a damper on Rhines’ sunny outlook for the industry he leads: “The third quarter last year was another great quarter for the EDA and IP industries. With 7.1 percent growth, it was really good and even stronger than usual.
Thursday, December 10th, 2015
If Wednesday night’s EDAC event at their headquarters in San Jose is any indication, things ain’t so good in the EDA ‘hood. There are no investors, no startups, no energy, no room for innovation, no luster, and ergo no young people.
Although, Jim Hogan – who shared the evening’s stage with Ansys/Apache VP & GM John Lee – said that if you think EDA’s bad, you should look at Google. According to Hogan, the luster’s gone at Google as well, buses transporting techies from Silicon Valley to their habitats elsewhere are running half empty, and nobody wants to be there anymore. The Google glam is gone, per Hogan, even though the overpaid youngsters he knows who work there are regularly pulling in salaries of $500k and holding an additional $500k in stock.
Hogan had no answer for how EDA was going to match those perks, but both he and Lee agreed that everything’s cyclical and therefore if everybody can just hold on for another 5 years, EDA will be back in fashion.
Meanwhile, it still ain’t so good in the EDA hood … or is it?
Thursday, November 5th, 2015
Since initiating their Decoding Formal Club in October 2013, Oski Technology has hosted this much-needed get-together every quarter, most recently on October 21st of this year at the Computer History Museum in Mountain View. I was fortunate to attend the debut meeting in 2013, so it was interesting to hear from Oski VP Jin Zhang that the support group is proving valuable to the growing numbers who attend.
“The first time we held the meeting,” Zhang said, “it was by invitation only, and we included about a dozen folks. Since that first event, we have continued to use the same room at the Computer History Museum, a room that can hold up to 40 people.
“The workshop, however, is continuing to grow very nicely, so we are faced with either finding a new venue or working with the museum to arrange for a bigger room for our next meeting in the first quarter of 2016.”
Zhang said interest in the event has increased to the point that people sign up to attend as soon as the date and time are announced. “They want to be sure they’ve got a spot,” she said.
Thursday, October 15th, 2015
Imperas Founder & CEO Simon Davidmann has been thinking about the EDA industry for a while, and the consortium that represents it. And like a lot of observers, he thinks change is in the air. In previous blogs, I myself have predicted that EDAC will evolve to offer better representation to IP providers, but Davidmann believes changes in the consortium will be even more dramatic.
“When EDAC was started,” Davidmann said in a recent phone call, “it was about CAD tools. But design automation has evolved from schematic layout and simulation to a point where everything is focused on really big designs. Yes, IP is a fundamental part of that evolution and companies like Synopsys have made a lot of investment in IP, so EDAC has no problem including IP in its landscape.
“But real problems today and tomorrow are about dealing with large systems on chips. Something that is moving the focus in the industry to software. Chip design is no longer just about design tools and IP, it’s about systems, and the software that runs on those platforms.
“As a consortium designed to help companies in the design automation business, therefore, EDAC has to look at not just design tools and IP. It also has to look at systems and software. An emerging technology, quickly moving into the mainstream, is virtual platforms for software development. Of course, Synopsys is investing in virtual platforms – an indication of the importance of such things in the design process.