Posts Tagged ‘Cadence’
Thursday, September 21st, 2017
Silicon Valley based Blue Pearl Software is the quintessential EDA company: privately held, run by a seasoned team of EDA experts, and with a portfolio that includes tools for generating timing constraints, CDC analysis, both synchronous and asynchronous, RTL verification tools for methodology standards and design rules, and design management tools.
Similarly, Blue Pearl’s Ellis Smith is the quintessential CEO in EDA. Before founding his current company, Smith was CEO and President of Orora Design Technologies, CEO at TransEDA through that company’s IPO in 2000, and CEO at Exemplar Logic through its merger with Mentor Graphics in 1995. His experience also includes a stint as CEO at CrossCheck Technology, and years spent at Duet Technologies, CADAM, Versatec, Dictaphone, and 3M. Pretty much the whole history of the EDA industry in one CV.
It would be an excellent idea to sit down for a very long conversation with Ellis Smith to discuss his take on the history of this oh-so-interesting industry. Unfortunately, time was of the essence when I did get the chance to talk with him earlier this month, and the focus was principally on Blue Pearl.
Wednesday, July 19th, 2017
Impersas CEO Simon Davidmann lead a tutorial at the Design Automation Conference last month in Austin. Prior to his presentation, we spoke by phone about the content of that tutorial.
“It’s a simple message we’re presenting at DAC,” Davidmann said, “but an important one. If you’re a semiconductor guy building a chip, your customers want to know what components are being used, but you also have to build the software that runs on top of it.
“There’s a lot of challenge, however, in getting an operating system up and running on the hardware and the problem extends to hardware-dependent software. Even the lowest level bits become part of the operating systems. So our tutorial is about what you need to do this work, about how to get hardware-dependent software running.”
Thursday, June 22nd, 2017
It’s impossible not to enjoy a fast-paced conversation with Upverter co-Founder and CEO Zak Homuth. Upverter offers a collaborative, cloud-based PCB design tool, and now this month has added EE Concierge.
Homuth started our recent phone call by referencing a conversation we had in 2015: “It’s been a long, hard fight since that time, but our new product is working well and we are excited about it. With it, we are shifting our focus even more towards on-demand engineering.
“Our new product – EE Concierge, the Electrical Engineering Concierge Service – is an evolution of the real-time, on-demand, virtual assistant for PCB engineers that we experimented with back in 2015.
“Now it’s a completely separate product that can be used by any hardware engineer in the world, with any ECAD tool like Altium or Eagle [Autodesk]. It’s not just for Upverter users, hardware engineers today – the people responsible for every new device you buy – have their own team of engineering assistants.”
I asked Homuth to define on-demand engineering.
Thursday, June 1st, 2017
Master technologist John Sanguinetti has made major contributions to the EDA industry in the first decades of his career, and is now doing the same for the IP industry. After finishing his PhD at University of Michigan, Sanguinetti worked at DEC, Amdahl, Elxsi, Ardent Computer, and NeXT, was President at Chronologic, Modellogic, and CynApps, and was CTO at Forte Design.
In 1990 while still at NeXT, Sanguinetti became convinced he could write a better simulator than Cadence’s VerilogXL, so working nights and weekends for several months he wrote VCS. The potential of the tool inspired Sanguinetti and Peter Eichenberger to found Chronologic. They launched the product in late 1992, and sold the company to Viewlogic in late 1994. Synopsys acquired Viewlogic in 1997, and VCS has continued on there as a foundational element of the company’s verification strategy.
Currently Sanguinetti is serving as Chairman at Adapt-IP, but given his long and distinguished history with EDA, he agreed to opine this week on Grand Challenges in EDA. In the following conversation, he offers two Grand Challenges in EDA and two in Security, the latter being an issue of rapidly growing concern worldwide.
Thursday, March 30th, 2017
Today is the day some EDA purists thought would never happen: The disassembling of an industry status quo that’s been in place for over 20 years
As of today, Mentor Graphics has been sold and is fully owned by Siemens. Now Mentor’s arc of history will be decided by folks not residing in the green forests and hills of northern Oregon, and the Big Three cartel is no more. A cartel which has slowly consolidated the playing field over time until nary a startup can be seen.
The power vested in the Big Three EDA companies has grown steadily and inexorably over these years, as has their market dominance. Examination of recent numbers provided by the ESD Alliance Market Statistics Service indicates that today, in excess of 85-percent of the revenue earned in the EDA industry can be attributed to the combination of Synopsys, Cadence, and Mentor Graphics.
These three companies, their leadership, sales prowess, and increasing control of the conversation and technical direction in the industry has made for a powerful cartel. But again, that cartel is no more and the crystal ball predicting future dynamics within the EDA industry has gone dark.
Thursday, March 23rd, 2017
Something historic and poignant is taking place on Thursday, April 6th, that should be of interest to absolutely everyone in the EDA and IP communities. The four most powerful men in these two industries will be on stage for an ESD Alliance panel discussion led by Semiconductor Engineering’s Ed Sperling.
The four panelists include Synopsys Chairman & CEO Aart de Geus, Cadence President & CEO Lip-Bu Tan, Mentor Graphics Chairman & CEO Wally Rhines, and ARM CEO Simon Segars.
The April 6th event will be historic because these Big Four unequivocally define EDA and IP – just as Stanford, Huntington, Hopkins, and Crocker defined Railroads in the West – and it’ll be poignant because you’ll never see them together again. Too many changes ahead.
Of course, the ESDA panel will also be whimsical: You’ll know no more about these CEOs and their companies at the end of the evening than you knew when you first arrived. That doesn’t mean the evening won’t be entertaining.
Thursday, March 9th, 2017
This is a simple post with just two messages. First, EDA is hiring. All over the globe. Mentor Graphics lists over 200 openings, Cadence has almost 300 openings, and Synopsys has a staggering 900+ openings worldwide.
Of course, EDACafe’s own Mark Gilbert could have told you this. It wasn’t necessary to scour the websites of the Big Three in EDA to learn about the many jobs currently available in the industry, most for software developers, not surprisingly.
Thursday, January 26th, 2017
Next week, DesignCon 2017 will be underway at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.
DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.
Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.
Also exhibiting this year at DesignCon will be our own EDACafe.
Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.
Thursday, January 5th, 2017
IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.
Unfortunately, the last several Kaufman Award dinners were such over-the-top events – the 2014 event in honor of Dr. Lucio Lanza awash in glamour and luminaries, and the 2015 event in honor of Dr. Walden Rhines replete with zany zeitgeist and a roast from Intel-legend Craig Barrett unparalleled in the annals of EDA history.
The organizers of this year’s event may, therefore, find it impossible to craft something anywhere close to the previous two dinners, if the metrics of energy and frenetic glad-handing are the only ones of importance.
Of course, these are not the only two metrics of importance and nothing is ever impossible in EDA or IP, so do not despair.
Thursday, October 13th, 2016
Congrats to the ESD Alliance for continuing to attend to myriad legal issues that surround the business of technology. On Tuesday, November 1st, the organization is hosting an evening panel on the Cadence campus entitled “Legal Steps to Maximize Your Exit Value.”
Vital topics slated for discussion include setting the proper price for intangible assets – in-house IP, strategic partnerships, and good will – and more prosaic issues such as the appropriate legal structures and pre-deal tax planning needed to help facilitate the acquisition. Most importantly, panel organizers are also promising you’ll learn “how to avoid giving it all back to your buyer later”.
Which is where our EDA M&A Hall of Fame comes in. There’s just no way this ESD Alliance panel can carry any weight with a battle-hardened EDA audience without the likes of Sanjay Srivastava, Rajeev Madhavan, Chris Rowen, and Kathryn Kranen sitting up at the front of the room.