Posts Tagged ‘Apache’
Thursday, September 28th, 2017
Vic Kulkarni is well-known in the EDA community as co-Founder, CEO and President of Sequence Design from 1995 until the company merged with Apache in 2009, which in turn was acquired by ANSYS in 2011. Kulkarni is now VP and Chief Strategist in the Office of CTO for the Semiconductor Business Unit at ANSYS.
There is little Kulkarni has not seen in his 30+ years in Silicon Valley. Although our conversation here mostly highlights current successes at ANSYS, it’s clear he continues to be wildly enthused about the broader promises of technology and the exciting efforts underway to create tools and strategies to bring those promises to fruition. Vik Kulkarni’s enthusiasm is the kind of thing that continues to make this industry so vibrant, and makes careers herein appealing for the next generation of engineers.
Thursday, December 10th, 2015
If Wednesday night’s EDAC event at their headquarters in San Jose is any indication, things ain’t so good in the EDA ‘hood. There are no investors, no startups, no energy, no room for innovation, no luster, and ergo no young people.
Although, Jim Hogan – who shared the evening’s stage with Ansys/Apache VP & GM John Lee – said that if you think EDA’s bad, you should look at Google. According to Hogan, the luster’s gone at Google as well, buses transporting techies from Silicon Valley to their habitats elsewhere are running half empty, and nobody wants to be there anymore. The Google glam is gone, per Hogan, even though the overpaid youngsters he knows who work there are regularly pulling in salaries of $500k and holding an additional $500k in stock.
Hogan had no answer for how EDA was going to match those perks, but both he and Lee agreed that everything’s cyclical and therefore if everybody can just hold on for another 5 years, EDA will be back in fashion.
Meanwhile, it still ain’t so good in the EDA hood … or is it?
Thursday, August 27th, 2015
Blogs are a dime-a-dozen, but you’re going to want to read this one if you want to know why distinguished veterans of EDA continue to evangelize for the viability and vitality of the industry.
On a phone call this week with Raul Camposano, newly-minted CEO of Sage Design Automation, and Coby Zelnik, President and Co-founder of the company, the point was driven home repeatedly: There’s as much of a future in EDA as there is a past, no matter what the current demographics may imply. Evolving demand in the CAD-tool marketplace means EDA companies will continue to emerge to meet that demand.
Thursday, September 26th, 2013
A Professor, a Sage, and a Guru walked into a bar. Brian the Bartender, greeted them: “What’ll it be, boys?”
The Professor said, “We need some help, Brian, settling an argument.”
“No problema,” Brian the Bartender said. “I’ve got an answer for everything.”
“Well,” the Professor said, “I think ESL’s not going to happen in our lifetime, but the Guru here says it’s just around the corner now that he and his have finally got all the pieces of the flow in place.”
Brian the Bartender laughed, “Yeah, the Guru’s been saying that since the dawn of mankind!”
“Exactly,” the Professor said.
Again Brian the Bartender laughed, “Guru, can you defend yourself? And don’t even think about plunking your wordy White Paper down on the bar. This is a public house, not a public library.”
Thursday, July 5th, 2012
The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?
Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …
… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.
This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?
Saturday, March 24th, 2012
When we last left our hero – that is, Mentor’s Catapult C high-level synthesis tool – it had just been sold off to Calypto in a move that the companies said, “will create a better integrated ESL hardware realization flow.”
Now, some 7 months into the adventure, I spoke with Calypto’s recently appointed VP of Marketing Shawn McCloud at DVCon:
Shawn: Calypto specializes in the ESL hardware implementation flow. We’re accelerating design with Catapult, optimizing the design for power efficiency with PowerPro, and doing verification with SLEC, which provides equivalence checking from RTL-to-RTL, or from C-to-RTL.
Q: Who’s the competition?
Shawn: Nobody has all 3 of these products, but within high-level synthesis, it’s Forte – and yes, we are the new Mentor. For power, the competition is Apache and Atrenta, but they’re both manual solutions, while we’re automated. And, nobody has our equivalence checking capability.
Q: Your exit strategy?
Shawn: Our goal is to grow 25-to-30%, year over year, and then we will have a number of different options: acquisition, or even an IPO.