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Posts Tagged ‘Ansys’

Emulation: Mentor & Ansys change the game

Thursday, July 16th, 2015

 

On May 27th, Mentor released its Veloce Power Application software, which “replaces a file-based power analysis flow with a Dynamic Read Waveform API integration to power analysis tools. [The new] approach captures information from the power switching activity plot and transfers that data to power analysis tools, [enabling] accurate power calculation at the system level, better power exploration at RTL for power budgeting and trade-offs, and more accurate power analysis and sign-off at the gate level.

“The [previous] approach of running the emulator, creating the file, reading the file into the power analysis tool, and running the power analysis tool is now reduced to just the emulator and power analysis run times.”

Several weeks after this announcement, I had a chance at DAC to meet with Jean-Marie Brunet, head of marketing for Mentor’s Emulation Division, and his team. We had a very interesting chat about the company’s progress with the Veloce technology.

Brunet was emphatic: “Mentor graphics is currently the global leader in emulation, with all others trying to play catch up but not succeeding! Our May 27th Veloce Power Application [is a reflection of that leadership].

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#52DAC Day Zero: Ten Astonishing Bits

Sunday, June 7th, 2015

 

Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.

So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:

10 — Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)

9 — EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!

8 — Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.

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EDAC CEO Panel: Practically perfection

Thursday, March 14th, 2013

 

From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.

Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.

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SI: What comes after CDNS acquires Sigrity?

Thursday, July 5th, 2012

 

The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?

Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …

… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.

This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?

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CST: Webinar series



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