Posts Tagged ‘Ansys’
Wednesday, January 20th, 2016
Just short of 2 years ago, the EDA press corps sat in a room in the Hyatt Regency in Santa Clara and enjoyed a face-to-face with Cadence CEO Lip-Bu Tan. A full report of that conversation is available here, but it is the closing segment of the report that informs this blog:
Finally, the Cadence PR machine closed out the hour by making sure the Press Corps was privy to the human side of CEO Tan. It would appear his wife does not make the tech-product purchasing decisions at home as much as do the two boys. Tan said that his two CMU-educated engineer sons are smart and savvy, and had advised him early on to invest in both Netflix and Tesla. Tan humbly acknowledged that he had, unfortunately, ignored those two pieces of advice and hence had lost out on the opportunity to win big in both movies and EVs.
So, here’s the hypothetical: Given Lip-Bu Tan’s involvement with a $2 billion investment group – efforts interleaved with his responsibilities as Cadence CEO – wouldn’t it have been wise to harvest stock tips from his press meeting back in March 2014 in Santa Clara?
Thursday, January 7th, 2016
If you’re interested in the past, the third quarter of 2015 is a good place to start: the EDA/IP industries did very well from July through September last year. EDAC’s Market Statistics Service numbers, released this week, offer some of the details. Here’s the link if you want to delve in.
Easier however, is this brief summary of my January 5th phone call with Mentor’s perpetually optimistic CEO Wally Rhines, last year’s EDAC/CEDA Kaufman Award winner and this year’s EDAC spokesman [technically, every year’s].
Although there was snow and ice on the roads around Wilsonville, Oregon, when we talked, nothing could put a damper on Rhines’ sunny outlook for the industry he leads: “The third quarter last year was another great quarter for the EDA and IP industries. With 7.1 percent growth, it was really good and even stronger than usual.
Thursday, December 10th, 2015
If Wednesday night’s EDAC event at their headquarters in San Jose is any indication, things ain’t so good in the EDA ‘hood. There are no investors, no startups, no energy, no room for innovation, no luster, and ergo no young people.
Although, Jim Hogan – who shared the evening’s stage with Ansys/Apache VP & GM John Lee – said that if you think EDA’s bad, you should look at Google. According to Hogan, the luster’s gone at Google as well, buses transporting techies from Silicon Valley to their habitats elsewhere are running half empty, and nobody wants to be there anymore. The Google glam is gone, per Hogan, even though the overpaid youngsters he knows who work there are regularly pulling in salaries of $500k and holding an additional $500k in stock.
Hogan had no answer for how EDA was going to match those perks, but both he and Lee agreed that everything’s cyclical and therefore if everybody can just hold on for another 5 years, EDA will be back in fashion.
Meanwhile, it still ain’t so good in the EDA hood … or is it?
Thursday, November 26th, 2015
It’s Thanksgiving and time to give thanks. Yes, we’re grateful for family, friends, and another year of opportunity in this tech-driven economy, but let’s also be grateful for EDAC. The Consortium is on a tear these days, offering programs, information, and networking with seemingly limitless zeal and energy.
Following two successful events in as many months – the Patents Panel in October and the Kaufman Award Dinner in November – EDAC is now offering in December another installment of their ongoing ‘Jim Hogan Emerging Companies Series.’ And given that EDAC’s food and wine in October and November were great, it’s pretty much guaranteed that this next event will really be gourmet. [hope, hope …]
But that’s not why EDAC’s December 9th event will be compelling; it’s the indefatigable Jim Hogan that will make it worth your while. Following a string of successful on-stage conversations over the last several years with seasoned EDA veterans such as Kathryn Kranen, Ravi Subramanian, and Joe Costello, the end-of-2015 edition will showcase Jim in conversation with Ansys GM & VP John Lee.
Thursday, September 3rd, 2015
Alain Labat, the former President & CEO of VaST Systems, told me on a phone call this week that his story, in a way, is very simple: “When we got acquired by Synopsys in 2010, 5 years ago now, our management and investors clearly saw an opportunity to start our own investment bank and advisory company, so that’s what we did.
“We believed then, and still believe, that if you need a big bank from New York or a huge amount of money [to begin your enterprise], the right people are the Goldman Sachs or the other Wall Street guys. But for a technology-based company, you need something different.
“And so, at the advice of our investors, we started Harvest Management Partners specifically for those companies who need something different. Coming from VaST as we did, with a great deal of true operational experience, we felt we could offer much-needed guidance to those companies who were not a good fit for Wall Street.
Thursday, August 27th, 2015
Blogs are a dime-a-dozen, but you’re going to want to read this one if you want to know why distinguished veterans of EDA continue to evangelize for the viability and vitality of the industry.
On a phone call this week with Raul Camposano, newly-minted CEO of Sage Design Automation, and Coby Zelnik, President and Co-founder of the company, the point was driven home repeatedly: There’s as much of a future in EDA as there is a past, no matter what the current demographics may imply. Evolving demand in the CAD-tool marketplace means EDA companies will continue to emerge to meet that demand.
Thursday, July 16th, 2015
On May 27th, Mentor released its Veloce Power Application software, which “replaces a file-based power analysis flow with a Dynamic Read Waveform API integration to power analysis tools. [The new] approach captures information from the power switching activity plot and transfers that data to power analysis tools, [enabling] accurate power calculation at the system level, better power exploration at RTL for power budgeting and trade-offs, and more accurate power analysis and sign-off at the gate level.
“The [previous] approach of running the emulator, creating the file, reading the file into the power analysis tool, and running the power analysis tool is now reduced to just the emulator and power analysis run times.”
Several weeks after this announcement, I had a chance at DAC to meet with Jean-Marie Brunet, head of marketing for Mentor’s Emulation Division, and his team. We had a very interesting chat about the company’s progress with the Veloce technology.
Brunet was emphatic: “Mentor graphics is currently the global leader in emulation, with all others trying to play catch up but not succeeding! Our May 27th Veloce Power Application [is a reflection of that leadership].
Sunday, June 7th, 2015
Omygosh, DAC’s here again! Has it already been a year? Apparently yes, and apparently once again the Design Automation Conference is going to be great. And how does one know? Because once again the DAC Executive Committee is great, lead in 2015 by the more-than-capable Anne Cirkel (Mentor’s own). Everything from academia to industry, from networking to hard-core learning (read, ‘Nerd Alert!)’, from food and libation to product announcements: DAC is always special.
So today is Sunday, which in the world of DAC is a lovely day full of workshops for those interested in the newest, and social opportunities for those interested in the noshing and nattering. Sunday is also lovely, because it’s a moment for astonishing realizations, and this year’s 52nd DAC Sunday is no different. Here are my 10 favs:
10 — Per Stanford’s Philip Wong speaking in Workshop 2, carbon nanotubes are smooth which helps with mobility-restricting surface roughness and band-gap issues. Also CNTs are no longer “a bowl of spaghetti” when manufactured. Now they’re 99% orderly and courteously aligned. (read, ‘Is asking about the other 1% a legitimate question?’)
9 — EDA’s own Karen Bartleson of SNPS fame, has not only just completed 2 years of distinguished service as President of IEEE’s worldwide Standards Organization, she’s now been nominated to serve as President of the Whole Enchilada; Bartleson’s running for President of the IEEE itself. In a word, Wow!
8 — Design Automation Summer School, for those who have not been keeping up (read, ‘me’), is no longer a week-long confab in July. These days Summer School is a one-day event on DAC Sunday. Still highly attended and full of pithy content for The Young & The Restless in EDA.
Thursday, March 14th, 2013
From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.
Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.
Thursday, July 5th, 2012
The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?
Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …
… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.
This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?