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Posts Tagged ‘AMD’

Accellera’s PSWG: Realists and Optimists, the lot of them

Thursday, March 17th, 2016

 


Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon
several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

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Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013

 

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

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Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

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Prakash Narain: creating a unique workplace culture at Real Intent

Thursday, June 13th, 2013

 

Every year, Forbes publishes a list of the Best Companies To Work For. The winners are always big companies, ones well known by you and me. The problem is that Forbes’ polling techniques are flawed. If they were not, EDA stalwart Real Intent would most definitely make the list, particularly if the folks from Forbes were to have been in on a recent phone call with Real Intent President & CEO Prakash Narain.

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OVPs: old ideas made new

Sunday, April 15th, 2012

 

Open Virtual Platforms are an idea whose time has arrived. That is, if you understand what they are. Certainly, if you’re reading this blog, you know what a virtual platform is.

“Platform virtual machines are software packages that emulate the whole physical computer machine, often giving multiple virtual machines on one physical platform.”

For additional clarity, check it out on Wikipedia, paying particular attention to the incredibly dense/complex table found there that attempts to catalog various virtual platforms, their origins, supporting organizations, and features.


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Imperas & Open Virtual Platforms

So, if that’s what virtual platforms are, then what are Open Virtual Platforms, OVPs?

Imperas – an enterprise founded in Silicon Valley in 2008 – would like you to understand and use OVPs. To do that, they are sponsoring a portal-based community called Open Virtual Platforms – a resource  designed to help chip developers have access to various open source virtual platforms, or models, of various commonly used hardware platforms endemic to the embedded systems world.

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