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Posts Tagged ‘Accellera’

Shishpal Rawat: Intel, CEDA, Accellera, Calm Commitment

Thursday, July 14th, 2016

 


Intel’s Shishpal Rawat has been Chair of Accellera for 6 years and is currently serving as President of CEDA
, IEEE’s Council on Electronic Design Automation. In previous discussions, Rawat has insisted that his leadership is not what makes these organizations work. Only the enthusiastic efforts of the many members guarantee that both Accellera and CEDA continue to shape ideas, standards, and forward progress within design automation and its adjacent technologies.

Two years ago, I enjoyed a lengthy interview with Rawat about all of this, described here. This year, I’ve chatted with Rawat at DVCon in San Jose in March, and again by phone just prior to DAC in June. During the phone call, Rawat focused on CEDA’s activities at DAC in Austin. He told me the upcoming Sunday night panel, set to be moderated by SRC’s Bill Joyner on June 5th, was a new and very exciting addition to the DAC program.

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Semifore: Celebrating 10 years with powerful CoStar Platform

Thursday, May 26th, 2016

 


Ten years ago, Rich Weber and Jamsheed Agahi
surveyed an industry they knew well – they each had 10+ years’ involvement in the technology – and found no one was providing hardware/software interface solutions. So in February 2006, they founded a company to “provide good solutions to the industry” and got busy coding. They had their software up and running by DAC, held that year in San Francisco, were featured in the July 2006 issue of EETimes, and were working with their first customers by the end of the year.

Those early successes were an indication of the credibility of Semifore Inc. and a reflection of the singular vision of founders who knew each other well; they had worked with together at various companies prior to 2006, Data General, Silicon Graphics, StratumOne and Cisco Systems. Starting Semifore together was the logical next step in their collaborations. Now ten years on, both founders are still with the company

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Accellera’s PSWG: Realists and Optimists, the lot of them

Thursday, March 17th, 2016

 


Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon
several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

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DVCon: A moment in time

Thursday, February 4th, 2016

 


On a phone call last week
with the DVCon 2016 General Chair, Synopsys’ Yatin Trivedi, and 2016 Technical Program Chair, eInfochips’ Ambar Sarkar, I was again reminded of two unalienable truths: DVCon is a labor of love for those who have been involved for so long, and without these people the conference simply would not exist.

DVCon is the granddaddy of all design and verification conferences. It’s been housed annually in Silicon Valley since before the beginning of time, this year from February 29 to March 3 at the DoubleTree Hotel. As inevitable a part of the yearly conference cycle as DVCon may be, however, always remember that nothing is forever.

Learning and networking opportunities like DVCon only exist because a group of over-achieving volunteers continue to infuse the event with their special brand of energy and credibility. The conference goes on and on, because of the selfless dedication of the folks who carve time out of their busy professional lives to lead it — to solicit, vet and assemble the technical program, and to solicit, vet and assemble the exhibition hall (a unique ‘science fair’ sort of a deal that opens every afternoon after the technical sessions have wrapped up for the day).

But these kinds of volunteers do not always step forward and even when they do contribute at this level, their efforts often go unnoticed. Hence, when you think of DVCon, remember to be grateful to the team that brings it to you. Nothing lasts forever, even if DVCon seems likes it could. End of sermon.

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Intel’s Shishpal Rawat: Multiple hats, Singular focus

Thursday, September 25th, 2014

 


Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat
, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.

Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.

He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”

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Accellera Systems Initiative: team effort & SystemC Library 2.3

Thursday, July 19th, 2012

 

This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.

I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.

Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”

I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.

“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence],  Jerome Cornet [STMicroelectronics],  Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

******************

1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 - The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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