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 What Would Joe Do?

Posts Tagged ‘Accellera Systems Initiative’

D&VCon: A labor of love for Krolikoski & Co.

Thursday, February 13th, 2014

 

If ever there was a year when you thought to attend DVCon, this should be it, according to a recent phone call with Cadence Fellow Stan Krolikoski, serving as General Chair for the second year in a row. That’s because DVCon 2014 will be serving up the D and the V in equal measure, and won’t be skewed towards the V in DVCon as it has been [perhaps] in the past.

Per Stan, “We’ve gotten feedback every year from attendees that they want more emphasis on design. They say they like verification, but they want more design, so last year I gave marching orders to the Technical Program Committee [headed by Paradigm Works’ Ambar Sarkar] that they should add more people on the review committee who represent design.

“It’s actually been a long time in coming. Although last year was the 25th anniversary of the conference, 10 years ago the name was changed to DVCon. Prior to that, it was HDLCon and the content reflected that name. When the name was changed to DVCon it was supposed to include both design and verification, but [functional verification emerged as the larger focus].”

That focus meant that those types of experts tended to dominate attendance, according to Stan, but that’s been fixed this year: “We will still have excellent functional verification sessions at DVCon – everything for the beginner through to the guru, it’s all there – but we will also have sessions on low-power design, on analog/mixed signal, and on system-level design, as well as IP integration. We’re clearly moving away from just verification in adding lots of design content to the program that’s of interest to our audience.”

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DAC 2013: Top 10 from Day 1 in Austin

Monday, June 3rd, 2013

 

The Design Automation Conference is mostly about People who need People, so my Top Ten list from Day 1 in Austin here at the 50th DAC is about just that: The Luckiest People in the World.


No. 10)
Rushing up to Room 18 on Level 4 of the Austin Convention Center to attend the DFM&Y Workshop at 9 am, only to find that I couldn’t get in because I hadn’t paid. Why is this disappointment on the list of favorites?

Because on my way back down to Level 1, I ran into Jill Jacbos who’s been working overtime here in Austin on behalf of Accellera Systems Initiative (Stan Krolikoski received the 2013 Leadership Award at the 7 am breakfast today), the North American SystemC Users Group Meeting (taking place all day today on Level 3), and Jim Hogans’ Hot Zone Party tonight at Austin City Limit’s Moody Theater.

Jim’s efforts, and those of the folks helping him, are all to raise money for his Heart of Technology charity, which is donating funds raised in Austin to CASA (Court Appointed Special Advocates) of Travis County, Texas. If you want to donate, you can do so at Jim’s website.

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DVCon 2013: There is such a thing as a free lunch!

Thursday, February 21st, 2013

 

You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.

If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.

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Master & Commander: DVCon’s Stan Krolikoski

Wednesday, February 6th, 2013

 

Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it’s about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It’s also the amount of time Stan’s been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.

When I spoke with Stan by phone earlier this week, I asked if he’s been to every single conference since then. He laughed and said, “Absolutely! Looking back to 1988 – despite all of the mergers, and the coming together of various conferences, and the end of the HDL wars – I’ve been to every one of them!”

There’s nobody else who’s been to them all? Stan laughed again, “I don’t think so. They’ve either retired, or left the industry. Although I do think Dennis Brophy has been coming for a long time, but probably not all the way back to the beginning.”

Where was the first conference held in 1988? Stan said, “It was in Newport Beach. Why? Who knows. Back in the day, a number of meetings were held in Newport Beach. Maybe it was a destination, or maybe it was because there were a lot of defense contractors in the area. Remember that VHDL-87 had just come out and the language had a connection to the Department of Defense.”

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Accolade Opps: January 18th and 31st deadlines loom

Thursday, November 22nd, 2012

 

If you are looking for an opportunity to express your satisfaction with a colleague’s contributions to the world you work in, two outstanding chances currently present themselves. But take care: The deadlines for submitting your nominations quickly approach.

First, Accellera Systems Initiative [a.k.a. Accellera] has set January 18th as the deadline for submitting nominations for its 2013 Technical Excellence Award. Per the organization: “The Award recognizes outstanding contributions in the creation of EDA and IP standards [which are then contributed to the IEEE Standards Association] by a member of an Accellera technical committee.

“Any individual who is a member of an Accellera technical committee is eligible to receive the award, which will be presented at Accellera Systems Initiative Day during DVCon 2013 next February in San Jose. Candidates may be nominated by the industry at large and are endorsed by Accellera committee members. To nominate an individual, visit Accellera.org.”

If you want to do something really dramatic, however, the EDA Consortium is currently accepting nominations for its annual EDAC/CEDA-sponsored Phil Kaufman Award, which these organizations frequently refer to as the Noble Prize of EDA.

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Accellera Systems Initiative: team effort & SystemC Library 2.3

Thursday, July 19th, 2012

 

This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.

I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.

Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”

I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.

“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence],  Jerome Cornet [STMicroelectronics],  Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.

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DVCon: You will be Tested

Friday, February 10th, 2012

 

Pay close attention. You will be tested on the following.

DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.

DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.

JL’s panel this year will include Ted Vucurevich, John  Costello (sic erat scriptum), Gary Smith, and Jim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM, SpringSoft, Xilinx, and Cadence.

DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled: Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.

DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.

Creating standards is another way of figuring out how we can all get along. Which brings us to Karen Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.

Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.

Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29th from 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.

She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should be planning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.

Speaking of money, DVCon is good there as well. They have made enough money to be profitable several years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.

Okay, if you’ve read carefully to this point, there’s only three things left to do.

* Register for DVCon.

* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012 Technical Program Chair and Tutorials & Panel Chair on February 16th.

* Take the quiz, which will be posted here on February 17th.

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