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Saturday, March 3rd, 2012
Tags: Alberto Sangiovanni-Vincentelli, Bosch, DAC, DATE 2012, Design Automation, Design Automation & Test in Europe, Dresden, Embedded Systems, Embedded World, GlobalFoundries, Klaus Meder, Mofy Chian, System-level design, Test, University of Tübingen, Wolfgang Rosenstiel
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Thursday, December 21st, 2017
Tags: AI, Apple, Applicon, ARM, Atari, Averant, Cadence, Calma, Commodore, Computervision, Daisy Systems, Dave Millman, EDA Consortium, EDA Systems, EDAC, Escalade, ESD Alliance, Go, IEEE 1801, IIT Chicago, Intel, Invionics, Mentor, Microsoft, Northstar, NVIDIA, Phil Kaufman Award, Qualcomm, RISC-V, Samsung, Sinclair, Steve Jobs, Synopsys, Synplicity, UPF 3.0, Valid Logic, Verific
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Thursday, December 7th, 2017
Tags: Alberto Sangiovanni-Vincentelli, Cadence Design Systems, Carnegie Mellon University, Center for Circuit and System Solutions, Charles Bunzli, Coursera, ESD Alliance, IEEE CEDA, John Cohn, Kaufman Award, Martin Wong, MOOC, Neolinear, Patrick Groeneveld, Ramesh Harjani, Rick Carley, Rob Rutenbar, Ron Rohrer, Tom Beckley, University of Illinois Urbana-Champaign, University of Minnesota, University of Pittsburgh, Voci Technologies Inc.
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Thursday, November 30th, 2017
Tags: Alberto Sangiovanni-Vincentelli, Cadence, Chenming Hu, Denali, ESD Alliance, Forte, Jasper, John Shoven, Lip-bu Tan, Moore's Law, Sigrity, Stanford, Tensilica, UC Berkeley, Walden International
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Thursday, November 2nd, 2017
Tags: HiSilicon, Hynex, ICScape, Jason Xing, Legend Designs Systems, LG, Marvel, Samsung, Tsinghua University, University of Illinois at Urbana-Champaign, University of Louisiana
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Thursday, November 2nd, 2017
Tags: Coby Hanoch, David Perlmutter, EDAcon Partners, Jasper, Leti Labs, memristor, ReRAM, Resistive random-access memory, Rice University, SiOx, Verisity, Weebit Nano
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Thursday, October 26th, 2017
Tags: DAC, DVCon, Eclipse, EDA, Emacs, ESD Alliance, Ghent, Hardware design, Hendrik Eeckhaut, Philippe Faes, Sigasi, Sigasi Studio, SystemVerilog, Verilog, VHDL
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