What Would Joe Do?
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
January 23rd, 2013 by Peggy Aycinena
Each time around, it’s an interesting exercise to see what conferences are being co-located with DAC, and this year is no different. From May 31st to June 2nd in Austin, the 2013 Electronic System Level Synthesis Conference [ESLsyn] will be co-located with the 50th Design Automation Conference. That’s a particularly interesting choice, because after so many years of ESL enthusiasts positioning system-level design at the center of all things EDA, why does it still need its own conference?
Well, let’s look at the organizers’ description of the meeting: “ESLsyn focuses on automated system design methods that enable efficient modeling, synthesis, exploration and verification of systems from high-level specifications down to lower level implementations.”
Okay. That’s sounds good. But, again, isn’t that stuff covered in a host of different sessions at DAC itself, in particular in Tracks EDA1 and EDA2?
January 22nd, 2013 by Peggy Aycinena
Several weeks into his new gig at Carbon Design Systems, it was a pleasure to speak by phone with Hal Conklin, VP of Sales and Marketing at the company. Conversationally, it was a bit of a random walk.
WWJD: Prior to joining Carbon, what were you doing?
Hal Conklin: I was doing enterprise software development for the government. I enjoyed the work, but not working for the government. I did that for 3 years and was quite successful, but it wasn’t something I wanted to do long term.
WWJD: So what inspired you to join Carbon?
Hal Conklin: I’ve been in EDA for quite a while and know how important it is to be with a company that has a product and customers who renew [their licenses]. Carbon is particularly important today with the changes that are coming in virtual prototyping. So given all the good stuff I’ve been seeing, I joined the company.
January 17th, 2013 by Peggy Aycinena
If you design boards or embedded software, you undoubtedly know Altium. You may not know, however, that these last several years have been a period of immense growth and change at the company. Following a corporate move to Shanghai in 2010, last year saw Altium’s revenue increase by 21 percent and a new executive team installed.
On a recent call, Altium CEO Kayvan Oboudiyat, CTO Aram Mirkazemi, and CMO Frank Hoschar described the philosophical underpinnings driving all of this change. Oboudiyat started with the view from 75,000 feet.
Kayvan Oboudiyat: Electronics is at the heart of a smarter world, and a smarter interface to the web and the design ecosystem, an Internet of Things emerging at the global level. Altium sees itself as a provider of tools and technology to the device-design ecosystem. We are part of the Internet of Things phenomenon, rather than an operator of it. The basic elements of the ecosystem, as we see it, are the CAD companies that provide the tools for design and a link to the [rest of the design chain].
January 16th, 2013 by Peggy Aycinena
There are three reasons why DAC will be spectacular come June in Austin: It’s the 50th instantiation of the conference; for the first time ever DAC is coming to the home of Office Space; and Synopsys Solutions Group Chief Architect Yervant Zorian will be General Chair, which means the 2013 Design Automation Conference has got the very best in the business at the top, a guy who’s CV includes leading committees of all shapes and sizes, IEEE Standards initiatives, and a variety of conferences, big and small.
Zorian’s track record in the industry is well known. My own article, Yervant Zorian: Grand Master of Time Management, was published on the DAC website in 2007. But all that said, it’s a personal recollection of Yervant Zorian that I prefer.
In 1999, I was tasked with writing my first Focus Report for ISD Magazine, a now-defunct publication of
January 10th, 2013 by Peggy Aycinena
EDA veteran Dr. Walden Rhines, Mentor Graphics CEO & Board Chairman, is one of the keenest and most optimistic observers of the industry. We spoke this week about the recent EDAC Market Statistics Service [MSS] numbers for Q3 2012.
Per Rhines: “EDA is growing at a rate almost a percentage greater than a year ago and most strongly in the Asia Pacific region, while also growing in other regions as well. [Only] Japan is not growing.”
He said there is growth in all product areas, but the “biggest growth is in the areas of new methodologies. ESL is very strong, and interestingly on the PCB side [growth was seen in] analysis tools such as signal integrity. But packaging is also growing, strongly consistent [with growth] in the new methodologies.”
Rhines also noted that CAE strength was largely influenced by growth in hardware-assisted verification (a.k.a. emulation), as well as the already mentioned ESL design.
“There’s actually healthy growth in everything,” he said, “except design verification and physical design and verification, which are both a little bit down. That’s largely caused by place-and-route, although detailed layout continues to be strong. [To be specific], the big category in physical design and verification is fine, and yield enhancement is fine, but standard place-and-route is weaker. If I had to come up with a reason, everything tends to have its ups and downs, so [in the long run] even place-and-route is still a good growth area.”
January 3rd, 2013 by Peggy Aycinena
As the New Year dawns, it is time to think about DAC 2013 happening from June 2nd to 6th in Austin, Texas. Of the many appealing aspects to the Design Automation Conference, the Designer/User Track that has been brought online over the last several years is one of the best. Hence it is important to note the deadline for submissions for the D/U Track is a brief month away — February 6th.
January 3rd, 2013 by Peggy Aycinena
Last night, Judy Collins gave a holiday concert at Davies Hall in San Francisco to a sold-out crowd of acolytes. Only an artist of Collins’ fame would be allowed to ofttimes warble off-key, forget the occasional lyric, and natter on in and around the music, yet still receive a standing ovation. After all, at 73 she is still full of performing fire, still full of attitude and life. Her appearance at Davies was a celebration of that life, lived to the fullest and in many different spheres.
Last week, U.C. Berkeley’s EECS Department threw a birthday party/symposium for Chenming Hu in Sutardja Dai Hall for an SRO crowd of past students, present students and acolytes, friends and family. Only an educator and technologist of Hu’s stature – former CTO of TSMC, ‘father’ of the FinFET, ‘godfather’ of BSIM and an international expert on CMOS device models – would be honored thusly in his 65th year by the University, and allowed to hand pick the list of speakers who filled the day-long event.
Not the least among those chosen was Ramune Nagisetty, a former MSEE student of Hu’s, who now leads a team at Intel/Hillsboro. Nagisetty recently added self-taught guitarist and vocalist/lyricist to her CV, and no matter that she ofttimes warbled off-key during her lunchtime and mid-afternoon performances during the symposium, and nattered on in and around her music, she still received a jumped-to-their-feet ovation from Hu et al.
That’s because Nagisetty was just one part of the evidence offered on December 13th – talks, demonstrations, and performances – to prove that Chenming Hu’s life to date has been lived to the fullest and in many different spheres: His family was in attendance to celebrate with the crowd, Hu’s paintings, and those of his wife and sons, were on display in the lobby outside Banatao Auditorium, Nagisetty’s music was presented, and a remarkable group of technologists as diverse as …
December 13th, 2012 by Peggy Aycinena
When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.
Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.
We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”
December 6th, 2012 by Peggy Aycinena
Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.
Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.
“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.
November 29th, 2012 by Peggy Aycinena
You’ve got a little over a week to clear your calendar to attend two very important conferences spanning the week of December 10th to the 14th. IEDM is happening in San Francisco from December 10th to 12th, and the 3-D Architectures for Semiconductor Integration and Packaging Conference is happening in Redwood City from December 12th to 14th.
These are two well-attended and carefully constructed conferences which many people attend to learn about the latest in device engineering and 3D-IC architectures, both key to the future of the semiconductor industry.
Clearly, December is a busy month. If you’re in Sales, you may be trying to maximize your numbers for the quarter, and the year, over the remaining weeks of 2012. If you’re in R&D, you may be trying to utilize budget dollars that come with ‘use it or lose it’ strings attached. If you’re in Field Support, your customers are stressed, short on time, and need your attention sooner, not later, so they can wrap up their projects before their holiday leave begins. And if you’re that customer, the Designer trying to meet a development schedule, you are really strapped for time.