What Would Joe Do?
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
February 14th, 2013 by Peggy Aycinena
In case you didn’t know, U.C. Berkeley is the center of the world. That’s why several hundred people attend the Berkeley EECS Annual Research Symposium each February, and this year is no exception. If you were here on campus with me this morning, you would be hearing – yet again – that there’s no better School of Engineering than Berkeley’s, no better EECS alumni than Berkeley’s, no better weather in the world than on this campus overlooking the glorious San Francisco Bay, and no more hip-or-hipster place to be. Anywhere.
BEARS 2013 started off today with Prof. David Culler acknowledging this year’s distinguished EECS Alumni Awards. Recipients include SanDisk Co-founder, President & CEO Sanjay Mehrotra; the co-inventor of a type of binary search tree, championship aerobatic pilot, and University of Washington professor Cecilia Aragon; and Sendmail developer Eric Allman, who mentioned from the podium that he may have helped create email but he’s not to blame for spam. Allman also noted that everybody who comes to Cal as a student is more lucky than smart to be here.
Yeah, right. How can that be the case if U.C. Berkeley continues to describe itself as the center of the technology universe, where swarms, networks, tablets, and big data, among a host of other innovations, were all developed and refined?
Having said these things, let me reminisce about my father, who by cosmic coincidence would turn 90 this week if he were still alive. Back in September 1940, when he was a desperately poor, 17-year-old fatherless child of the Depression, he showed up in this town to pursue a degree in biology and hopefully become a doctor. His widowed mother had lost the family’s 10 acres of orange trees, their only source of income, to the foreclosure agents of the Bank of Italy back in 1935, and my father brought that humiliation to Berkeley with him, along with 2 pencils, a pen, and one shabby change of clothing.
February 6th, 2013 by Peggy Aycinena
Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it’s about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It’s also the amount of time Stan’s been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.
When I spoke with Stan by phone earlier this week, I asked if he’s been to every single conference since then. He laughed and said, “Absolutely! Looking back to 1988 – despite all of the mergers, and the coming together of various conferences, and the end of the HDL wars – I’ve been to every one of them!”
There’s nobody else who’s been to them all? Stan laughed again, “I don’t think so. They’ve either retired, or left the industry. Although I do think Dennis Brophy has been coming for a long time, but probably not all the way back to the beginning.”
Where was the first conference held in 1988? Stan said, “It was in Newport Beach. Why? Who knows. Back in the day, a number of meetings were held in Newport Beach. Maybe it was a destination, or maybe it was because there were a lot of defense contractors in the area. Remember that VHDL-87 had just come out and the language had a connection to the Department of Defense.”
February 4th, 2013 by Peggy Aycinena
Breker Verification Systems VP Tom Anderson presented a concise tutorial on low-power SOC verification at DesignCon on January 30th. He began by laying out the challenges of low-power design, with an eye to the verification problems associated with various strategies:
The need for low-power design is ubiquitous, with today’s plethora of consumer devices being battery-powered. ‘Big iron’ machines in modern data centers are also driving the need for low-power chips. As well, governments worldwide – especially in Europe – are passing ‘green’ laws; if you’re building a ‘big iron’ class of machine, you may be required by law to meet specified power limits.
There are various techniques emerging to meet these needs. Circuit-level design strategies include special transistor and cell design for non-critical paths. Different voltage thresholds are also an option, yielding a variety of performance levels and power consumption at different points on-chip; designers can make a one-time trade-off between performance level and path options on-chip. These techniques have little or no impact on functional verification. Other strategies, however, do.
January 31st, 2013 by Peggy Aycinena
Just past 8:00 am in the Santa Clara Convention Center on Wednesday, January 30th, I had the good luck to run into IEC’s Dr. Barry Sullivan, long-time leader at DesignCon. Conversation’s always relaxed in that hour at any conference, and so it was with Barry. I asked him how things go with DesignCon, now that it’s owned and operated by UBM.
[Barry’s tenure with the conference predates the 2010 purchase of the conference by UBM, discussed here in a blog posted at the time by former EE Times Editor Nic Mokhoff.]
Barry said that UBM’s skill set is exactly aligned with the needs of DesignCon, and that’s a good thing. He said having a media company like UBM in charge is excellent for the conference. In the years prior to the acquisition, Barry said, the conference would sometimes have to “beg” the press to cover the event. With UBM at the helm, however, he said press coverage has been stupendous. I asked Barry if he thought DesignCon was out to replace DAC.
January 23rd, 2013 by Peggy Aycinena
Each time around, it’s an interesting exercise to see what conferences are being co-located with DAC, and this year is no different. From May 31st to June 2nd in Austin, the 2013 Electronic System Level Synthesis Conference [ESLsyn] will be co-located with the 50th Design Automation Conference. That’s a particularly interesting choice, because after so many years of ESL enthusiasts positioning system-level design at the center of all things EDA, why does it still need its own conference?
Well, let’s look at the organizers’ description of the meeting: “ESLsyn focuses on automated system design methods that enable efficient modeling, synthesis, exploration and verification of systems from high-level specifications down to lower level implementations.”
Okay. That’s sounds good. But, again, isn’t that stuff covered in a host of different sessions at DAC itself, in particular in Tracks EDA1 and EDA2?
January 22nd, 2013 by Peggy Aycinena
Several weeks into his new gig at Carbon Design Systems, it was a pleasure to speak by phone with Hal Conklin, VP of Sales and Marketing at the company. Conversationally, it was a bit of a random walk.
WWJD: Prior to joining Carbon, what were you doing?
Hal Conklin: I was doing enterprise software development for the government. I enjoyed the work, but not working for the government. I did that for 3 years and was quite successful, but it wasn’t something I wanted to do long term.
WWJD: So what inspired you to join Carbon?
Hal Conklin: I’ve been in EDA for quite a while and know how important it is to be with a company that has a product and customers who renew [their licenses]. Carbon is particularly important today with the changes that are coming in virtual prototyping. So given all the good stuff I’ve been seeing, I joined the company.
January 17th, 2013 by Peggy Aycinena
If you design boards or embedded software, you undoubtedly know Altium. You may not know, however, that these last several years have been a period of immense growth and change at the company. Following a corporate move to Shanghai in 2010, last year saw Altium’s revenue increase by 21 percent and a new executive team installed.
On a recent call, Altium CEO Kayvan Oboudiyat, CTO Aram Mirkazemi, and CMO Frank Hoschar described the philosophical underpinnings driving all of this change. Oboudiyat started with the view from 75,000 feet.
Kayvan Oboudiyat: Electronics is at the heart of a smarter world, and a smarter interface to the web and the design ecosystem, an Internet of Things emerging at the global level. Altium sees itself as a provider of tools and technology to the device-design ecosystem. We are part of the Internet of Things phenomenon, rather than an operator of it. The basic elements of the ecosystem, as we see it, are the CAD companies that provide the tools for design and a link to the [rest of the design chain].
January 16th, 2013 by Peggy Aycinena
There are three reasons why DAC will be spectacular come June in Austin: It’s the 50th instantiation of the conference; for the first time ever DAC is coming to the home of Office Space; and Synopsys Solutions Group Chief Architect Yervant Zorian will be General Chair, which means the 2013 Design Automation Conference has got the very best in the business at the top, a guy who’s CV includes leading committees of all shapes and sizes, IEEE Standards initiatives, and a variety of conferences, big and small.
Zorian’s track record in the industry is well known. My own article, Yervant Zorian: Grand Master of Time Management, was published on the DAC website in 2007. But all that said, it’s a personal recollection of Yervant Zorian that I prefer.
In 1999, I was tasked with writing my first Focus Report for ISD Magazine, a now-defunct publication of
January 10th, 2013 by Peggy Aycinena
EDA veteran Dr. Walden Rhines, Mentor Graphics CEO & Board Chairman, is one of the keenest and most optimistic observers of the industry. We spoke this week about the recent EDAC Market Statistics Service [MSS] numbers for Q3 2012.
Per Rhines: “EDA is growing at a rate almost a percentage greater than a year ago and most strongly in the Asia Pacific region, while also growing in other regions as well. [Only] Japan is not growing.”
He said there is growth in all product areas, but the “biggest growth is in the areas of new methodologies. ESL is very strong, and interestingly on the PCB side [growth was seen in] analysis tools such as signal integrity. But packaging is also growing, strongly consistent [with growth] in the new methodologies.”
Rhines also noted that CAE strength was largely influenced by growth in hardware-assisted verification (a.k.a. emulation), as well as the already mentioned ESL design.
“There’s actually healthy growth in everything,” he said, “except design verification and physical design and verification, which are both a little bit down. That’s largely caused by place-and-route, although detailed layout continues to be strong. [To be specific], the big category in physical design and verification is fine, and yield enhancement is fine, but standard place-and-route is weaker. If I had to come up with a reason, everything tends to have its ups and downs, so [in the long run] even place-and-route is still a good growth area.”
January 3rd, 2013 by Peggy Aycinena
As the New Year dawns, it is time to think about DAC 2013 happening from June 2nd to 6th in Austin, Texas. Of the many appealing aspects to the Design Automation Conference, the Designer/User Track that has been brought online over the last several years is one of the best. Hence it is important to note the deadline for submissions for the D/U Track is a brief month away — February 6th.