Archive for the ‘Uncategorized’ Category
Thursday, February 23rd, 2017
Accellera has just announced that Lu Dai, Senior Director of Engineering at Qualcomm, is the new chair of the organization.
Although Intel’s Shishpal Rawat, recently retired from Intel, is a hard act to follow as Accellera Chair given his long, productive years leading the organization, if anyone can do it Lu Dai can. He’s enthusiastic, energetic, optimistic, and an engineer – and not necessarily in that order.
Before talking about Accellera in our phone call this week, Dai spoke about DVCon, anchor tenant of Accellera’s outreach to design and verification engineers around the world. This next week, the Silicon Valley version will unfold in San Jose, with DVCon India happening in September, DVCon Europe in October, and the first-ever DVCon China in April.
Thursday, February 16th, 2017
Ted Miracco is CEO of SmartFlow Compliance Solutions, a company based in Los Angeles that provides automated tools to help software vendors combat piracy, copyright infringement, and under-compliance. At the company’s recent Anti-Piracy Summit, Miracco was impressed by four specific concerns of executives attending from the EDA and IP industries. The following blog, contributed by Miracco, describes those issues.
The Four Hacking Issues Weighing on the Minds of EDA Executives
I like spending time with executives from the EDA industry, in part because I used to be an executive in that industry. Last fall at the SmartFlow Anti-Piracy Summit, I had conversations with a dozen or so executives and heard a new urgency in their voices for help solving the challenge of unauthorized use of software and semiconductor IP.
Thursday, February 9th, 2017
Thanks to the staff of EDACafe, yet more video interviews are now available on the website. This content, recorded at last week’s DesignCon, continues to capture the technical expertise of those who pursue market excellence with today’s technology.
Those interviewed include: TE Connectivity’s Nathan Tracy, Rambus’ Mohit Gupta, Anritsu’s Joe Mallon, CST’s Klaus Krohne, Keysight Technologies’ Stephen Slater, DVT Solutions’ Brian Shumaker and Signal Microwave’s Bill Rosas, Mentor’s Dave Kohlmeier, ESD Alliance’s Bob Smith, Cadence’s Sam Chitwood, and Asteelflash’s Matheiu Kury.
You can see all of the DesignCon 2017 videos here.
Also of interest this year at DesignCon in Santa Clara, Steve Yamaguma was the winner of the Amazon Echo offered in a raffle in the EDACafe booth at the show.
Thursday, February 2nd, 2017
If you’re going to chair a conference, according to DVCon 2017 General Chair Dennis Brophy, don’t do any work. Instead just delegate, because if you’ve done that properly, the committees will craft a great program and a great gathering.
Hence, per Brophy, this year’s DVCon is going to be great. He’s done nothing, the committees have done everything, and their work has been inspired.
You must bring something to the effort, I insisted.
Brophy chuckled and deflected my question: “I’ll defer to Wally Rhines’ thesis: The learning curve definitely doesn’t stop, even though Moore’s Law is slowing. And there will be a lot of opportunity to learn this year at DVCon.
Thursday, January 26th, 2017
If you were to attend only one Kaufman Award dinner throughout your career, tonight’s might have been the right choice: a lovely meal in downtown Silicon Valley, and presentations full of warmth, respect, humor and clear-eyed admissions, all in honor of CMU’s Dr. Andrzej Strojwas, long-time CTO at PDF Solutions.
Having interviewed Prof. Strojwas some months ago when he was first named the 2016 Kaufman Award winner, and knowing the event was in the capable hands of the ESD Alliance, this evening’s ambiance was not a complete surprise. But the display of emotion and palpable affection with which Dr. Strojwas is held by colleagues and family was almost mesmerizing.
In fact, as PDF CEO John Kibarian hit his stride at the podium, detailing the lifetime of achievements and leadership at the core of Dr. Strojwas’ award commendation, there could be no looking away.
Thursday, January 26th, 2017
Next week, DesignCon 2017 will be underway at the Santa Clara Convention Center. As always, the program will include a lot of practical advice across a variety of design silos: Analog & mixed-signal modeling and design; modeling and analysis of interconnects.; PCB design, simulation, and fabrication; chip/package design and signal integrity considerations; EM interference; and various aspects of high-speed design.
DesignCon clearly continues to provide a learning venue for working engineers who deal with real-world problems, and again this year there will also be a lively exhibit hall.
Featured among the 185 exhibitors will be multiple companies offering tools for design – Cadence, Altium, Ansys, SiSoft, Mentor Graphics, Applied Simulation, EMA, DipTrace, Polar Instruments, SPISim, Valydate, XJTAG, and SpeedIC, among them.
Also exhibiting this year at DesignCon will be our own EDACafe.
Sanjay Gangal, President of IBSystems, and his team will be in Booth #1349 where they will be recording video interviews.
Thursday, January 19th, 2017
Synopsys is undergoing a massive reset. Where not so long ago, it self-identified as the largest EDA company in the world, other words are now used to describe the enterprise: “Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing.”
As compelling as that description may be, some observers are questioning whether the marked differences between maintaining expertise in chip design, verification, IP, and IP integration versus maintaining expertise in software integrity are too wide to make for easy co-habitation under one corporate roof.
Some would say putting EDA and chip design together with software security is not a good recipe for the long-term success of the company. But are these critics correct?
Thursday, January 12th, 2017
As we embrace a New Year, it is always a toss-up as to whether we are drawn to look to the past to understand our future, or to the future itself. The blank page. The untested waters. The mysterious frontier. Danger and opportunity seemingly mixed in equal proportions within the murky fog a-swirl in that not-so-crystal ball.
It’s within that spirit that I recalled this week a reverie that unfolded several years back while sailing the waters of Lake Gatun midst the Panama Canal. A reverie that attempted to synchronize the muscular optimism at the turn into the last century with the somewhat more tenuous outlook at the turn into this one.
That earlier reverie was tempered by remembering innovations such as the Vienna Secession, Futurism, Fin de siècle, Dada and Cubism – movements that propelled some observers from the nineteenth century into the twentieth – could hardly be said to reflect a stridently cheery outlook. Inversely, the angst and anxiety that oft-times characterize the narcissism of our own here-and-now – trends that have sometimes accompanied our complex journey from the twentieth century into the twenty-first – are profoundly repudiated by the engineering marvels that define this equally muscular New Age.
In truth, the past was never as rosy as we remember and rarely does the future fulfill our darkest premonitions. It’s simply the nature of the human comedy that we so thoroughly believe they do.
Thursday, January 12th, 2017
Are you building the IoT? Then you already know it’s a jungle out there.
Happily, the University of New Hampshire is offering an interesting service that should help. They’ll test your IoT device to see if it meets current Internet Protocal standards. Of course, understanding such a service presumes there are any standards in the first place – there are many, some very controversial – and also presumes you know how those standards are described within a veritable jungle of acronym-laden jargon.
But before we run through that rain forest of gobbledygook, let’s first review what the goals of the UNH InterOperability Lab are in establishing their IoT IP Testing Service. Those goals were laid out during an online press conference in December when the folks at the lab explained what they want to accomplish: Foster industry-wide collaboration, provide an extensive testbed for evaluating IoT devices, and train the engineers of tomorrow who want to help build the IoT.
These are clearly commendable goals, and the people behind the effort seem nothing if not cheerful and upbeat, but to fully understand what they’re doing you’ll first need to slog through the acronyms. Buckle your seat belt, it’s going to be a bumpy ride.
Thursday, January 5th, 2017
IEEE’s CEDA and the ESD Alliance – with help from their friends at PDF Solutions, Cadence, Mentor, Synopsys and ACM SIGDA – will host a dinner on Thursday, January 26th, in honor of the 2016 Phil Kaufman Award recipient: Dr. Andrzej Strojwas, Keithley Professor of ECE at Carnegie Mellon and long-time CTO at PDF Solutions.
Unfortunately, the last several Kaufman Award dinners were such over-the-top events – the 2014 event in honor of Dr. Lucio Lanza awash in glamour and luminaries, and the 2015 event in honor of Dr. Walden Rhines replete with zany zeitgeist and a roast from Intel-legend Craig Barrett unparalleled in the annals of EDA history.
The organizers of this year’s event may, therefore, find it impossible to craft something anywhere close to the previous two dinners, if the metrics of energy and frenetic glad-handing are the only ones of importance.
Of course, these are not the only two metrics of importance and nothing is ever impossible in EDA or IP, so do not despair.