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DAC 2013: Innovation Square

Thursday, March 21st, 2013


It’s time to start exploring what’s coming up at DAC 2013 in Austin the first week in June, and one way to do that is to visit the conference website. There you’ll find a variety of interesting things including an interactive Exhibit Hall map, which allows you to run your mouse over any booth and see which company’s going to be located there. Maybe that feature’s been available in years past, but it’s still pretty cool.

Something that certainly is new this year at DAC, however, is Innovation Square. I’ve boldly cut-and-pasted the graphic from the DAC website into this blog so you can see what it entails, which is this: You pay the DAC organization $5500 and for that you get a kiosk-like space, a 24-inch computer monitor, an electrical hook-up for your other stuff, booth-unit graphics, a shared private meeting suite with a schedule that you’ll know in advance, and one paid-in-full conference registration.

In other words, you get a “turn key package” that allows you to have a foot on the ground at DAC without enduring the mystery of “What’s this all going to actually cost me?” True, it looks like any particular company in Innovation Square only has about 15 or 20 square feet of show floor, but if otherwise you couldn’t afford to be on the show floor at all in Austin, this is a great innovation indeed.


EDAC CEO Panel: Practically perfection

Thursday, March 14th, 2013


From the podium in San Jose’s DoubleTree Hotel, Jasper Design Automation President & CEO Kathryn Kranen introduced tonight’s EDAC CEO Forecast Event as being “practically perfection” and she was right. With 97 people in the room, the event ran for 97 minutes and the audience [undoubtedly] gave the panel discussion a 97% approval rating. Kudos to all involved, including EDAC for hosting, and OCP-IP, Mod Marketing, and the DoubleTree for sponsoring the event.

Kranen started off the evening by bragging on good news out of EDA: It’s up and to the right for revenue in the industry, with a 4.9 percent increase between 3Q11 and 3Q12. She cited increased stock valuations over the last year for ARM [37%], Cadence [30%], Mentor [26%], PDF Solutions [98%], and Synopsys [17%] as an indication of the viability of EDA as an investment vehicle: If you’d put $100 into each of these companies a year ago, she said, you would have netted a 41% increase in a portfolio today worth $706.90, beating out other investment indices such as the NASDAQ and S&P 100 over the same time period.


ISQED 2013: IBM lays it on the line

Thursday, March 7th, 2013


IBM’s Brad Brech gave one of the Tuesday morning keynotes at ISQED 2013 on March 5th. It was a thought-provoking talk and well received by a large audience of engineers at the Techmart in Santa Clara. Per Brech, like everywhere in computing the trend in data centers is “smaller, cheaper, and faster.”

To illustrate, he drew comparisons with developments in aeronautics over the last century, invoking the Wright Brothers’ aircraft, the Curtiss Flying Boat, the Boeing Stratoliner, the De Havilland Comet, the Boeing 707, and the Concorde. All of these aircraft, he said, addressed technology concerns related to speed. As tragically illustrated by the Concorde disaster in 2000, however, eventually speed as a lone metric of progress in commercial aviation proved unsustainable. Instead, after 2000 the industry became more concerned about efficiency and less about speed.

Similarly, Brech argued, now for the first time in the history of computing, “While CEOs are identifying technology as the single most important external force impacting their organizations, they’re not interested in the speed of the technology but how quickly and efficiently it can be brought online. Now the IT cycle is about speed to adoption and efficiency, not just about the latest/greatest software or hardware.”


Great Circle: from ISQED to DATE

Thursday, March 7th, 2013


If you were lucky enough to be at the ISQED Poster Session in Silicon Valley on Tuesday afternoon, March 5th, you had a chance to speak with various university students presenting novel work, various industry researchers presenting new ideas, and Chi-Foon Chan, Co-CEO of Synopsys, whose long involvement with ISQED, and deep and abiding interest in the underlying technology, fueled lively conversations as he too visited posters being presented by academia and industry alike.

As well, you would have had a chance to speak with Prof. Daniela De Venuto from the Politecnico di Bari. She told me about her research into implanted devices which monitor rate of chemical absorption in the digestive tract, and ways in which the resulting data could impact our understanding of the biochemistry of drug delivery mechanisms.

She also told me about various fascinating sessions at the upcoming DATE 2013 conference in Grenoble, starting on March 18th. These sessions are of particular merit for anyone interested in the interface between biological systems, electronic systems, environmental systems, and all manner of collaborative research embracing them all.

On March 21st, Prof. De Venuto is chairing a session on Smart Health along with U.C. Berkeley Prof. Alberto Sangiovanni-Vincentelli. The session is part of a Special Day on Electronic Technologies for Smart Cities.


DVCon 2013: in 25 words per sound bite [or less]

Thursday, February 28th, 2013


I don’t know about you, but I thought DVCon 2013 in San Jose this week was super. There was a lot of energy, I never heard anybody say the tools are broken (something industry pundits have been droning on about for years), attendance at the conference set a new record, both verification and design guys seemed to indicate that verification is still important enough to remain discrete from design, and SystemVerilog is fulfilling its promise.

The following list of 15 sound bites is not a complete representation of all that was said or debated at DVCon. Nonetheless, it’s an interesting list and reflects some of the information and opinions showcased during the week.


DVCon 2013: Best Practices in Verification Planning

Thursday, February 28th, 2013


Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”

Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.


Verific Design Automation: Standing tall

Thursday, February 21st, 2013


If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.

Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”

I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”


DVCon 2013: There is such a thing as a free lunch!

Thursday, February 21st, 2013


You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.

If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.


Celebrations underway: Lynn Conway & Carver Mead

Thursday, February 14th, 2013


These several months are a great time to learn how the innovations of Lynn Conway and Carver Mead influenced the arc of history of the microelectronics industry.

The entire fall issue of IEEE’s Solid State Circuits Magazine is dedicated to Lynn Conway’s contributions to VLSI design and manufacturing. Monday morning, February 18th, Carver Mead will be keynoting at the opening plenary session of ISSCC in San Francisco. And next month at DATE 2013 in Grenoble, a panel entitled “The Heritage of Mead & Conway” will take place in Tuesday, March 19th.

The DATE panel will be moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, and will include IMEC’s Hugo de Man, Synopsys’ Antun Domic, U.C. Berkeley’s Jan Rabaey, CMP’s Bernard Courtois, and Columbia’s Luca Carloni. Per the conference program, the panel will discuss “what has remained the same [since the Mead-Conway VLSI Revolution], what was missed, what has changed, and what lies ahead.”


BEARS 2013: Cheerleading the way into the New Millennium

Thursday, February 14th, 2013


In case you didn’t know, U.C. Berkeley is the center of the world. That’s why several hundred people attend the Berkeley EECS Annual Research Symposium each February, and this year is no exception. If you were here on campus with me this morning, you would be hearing – yet again – that there’s no better School of Engineering than Berkeley’s, no better EECS alumni than Berkeley’s, no better weather in the world than on this campus overlooking the glorious San Francisco Bay, and no more hip-or-hipster place to be. Anywhere.

BEARS 2013 started off today with Prof. David Culler acknowledging this year’s distinguished EECS Alumni Awards. Recipients include SanDisk Co-founder, President & CEO Sanjay Mehrotra; the co-inventor of a type of binary search tree, championship aerobatic pilot, and University of Washington professor Cecilia Aragon; and Sendmail developer Eric Allman, who mentioned from the podium that he may have helped create email but he’s not to blame for spam. Allman also noted that everybody who comes to Cal as a student is more lucky than smart to be here.

Yeah, right. How can that be the case if U.C. Berkeley continues to describe itself as the center of the technology universe, where swarms, networks, tablets, and big data, among a host of other innovations, were all developed and refined?

Having said these things, let me reminisce about my father, who by cosmic coincidence would turn 90 this week if he were still alive. Back in September 1940, when he was a desperately poor, 17-year-old fatherless child of the Depression, he showed up in this town to pursue a degree in biology and hopefully become a doctor. His widowed mother had lost the family’s 10 acres of orange trees, their only source of income, to the foreclosure agents of the Bank of Italy back in 1935, and my father  brought that humiliation to Berkeley with him, along with 2 pencils, a pen, and one shabby change of clothing.


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