Archive for the ‘Uncategorized’ Category
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
Wednesday, August 28th, 2013
Perfectly suited by nature to teaching, when affable Cliff Cummings steps up to conduct his Verilog course, the class is in for a treat. From the get-go, Cliff establishes a tone of respect, humor, and openness to questions of any kind. He encourages students to interrupt when they don’t understand, to stand up, sit down, resort to coffee and/or carbs, and in all ways to relax and enjoy the learning experience.
There’s something additional, however, that Cliff brings to his inspired task of teaching and that’s his decades of involvement with the Verilog language, its evolution, standards, and implementation. What Cliff Cummings doesn’t know about Verilog and SystemVerilog, isn’t worth knowing. Period.
This week, Cliff is teaching Verilog-2001 Design & Best Coding Practices in Silicon Valley – specifically, in the offices of EDA Direct – and I’ve been lucky enough to attend. Not being a Verilog expert, I approached the class with some trepidation, but found to my delight that I was not the only one among the 8 engineers in the room “new” to the language. We’re all engineers, but we’re not all Verilog designers and hence it’s a class perfectly suited to our skills, interests, and goals.
Thursday, August 15th, 2013
Kevin Steptoe is VP of Engineering at Sondrel, a global chip-design consultancy based in Reading, U.K. We spoke this morning by phone about the future of FinFETs, in particular Steptoe’s reaction to my blog posted earlier this month, FinFETs: Yes, No, Maybe.
Steptoe said there’s nothing maybe about FinFETs. They are most definitely “an absolute yes” – revolutionary and disruptive as they may be – and offer great promise for the future of chip design, manufacturing, and deployment. And he said, his enthusiasm for the technology is not just from Sondrel’s point of view, but from his own personal involvement in the industry that extends back several decades.
Per Steptoe: “As the world’s increasingly insatiable demand for mobile, tablet-based, higher frequency devices ramps up, the predominant challenges for engineers and designers translate into fears of leakage power and performance. The FinFET, in its construction, addresses these challenges and makes mobile devices dramatically more possible.
“[In fact], the control of the short-channel affect and suppression of leakage actually simplifies things, so engineers will have the opportunity to achieve much higher [transistor] density, much lower power, and similar-or-increased performance levels. We see FinFETs as a win all the way around, a no-brainer that will fully live up to what it says on the tin: With FinFETS you will design ever larger devices with an ever higher power profile.”
Wednesday, August 7th, 2013
Well, it looks like the industry has done it again, delivering good growth over a recent quarter. The Press Release issued by EDAC’s Market Statistics Service on August 6th detailed the numbers for Q1_2013: 8.1% growth overall, including 23.8% growth in Services, 20.2% growth in IP, and (a bit less glam) 2.4% growth in EDA. Interesting.
Meanwhile, Dr. Wally Rhines continues to contribute to the industry by making himself available for conversation about the MSS numbers as they are released each period, clarifying as always that his comments are on behalf of EDAC and do not reflect his role as CEO of Mentor Graphics. When I spoke by phone with Rhines earlier this week, I asked him if we can anticipate industry results for all of 2013 by looking at the Q1 numbers.
He said no, EDAC numbers do not portend the future, they only aggregate the results from the past. To know more about the future of the industry, Rhines referred me to the four visionary keynotes given at DAC by Synopsys’ Aart de Geus, Cadence’s Lip-Bu Tan, Jasper’s Kathryn Kranen and Rhines’ own talk.
Thursday, July 25th, 2013
Ed Sperling, Editorial Director for Semiconductor Manufacturing and Design Community, moderated a breakfast panel on Tuesday morning, June 4th, at DAC. Having missed the bulk of the event, I was fortunate to have a chance later to review the slides of the five speakers: Cavium Networks VP Anil Jain, GlobalFoundries VP Subramani Kengeri and Director Kelvin Low, and Synopsys VP Raymond Leung and Senior Director Bari Biswas.
Having now gone through the slide deck twice, I’ve come away with a set of conflicting messages. On the one hand, the challenges of FinFET implementation are so great there is still much to be done, and the promise of the technology is yet to be fully proven. On the other hand, the synergy between GlobalFoundries and Synopsys is so excellent the challenges associated with FinFET implementation are definitely being met. So which is the more accurate message?
Tuesday, July 16th, 2013
Sitting in beautiful Boston on a sunny morning in July, with Cambridge just across the Charles River, it is a wistful exercise to contemplate the life of Amar Bose. Given that Dr. Bose was a well-known professor at MIT and an equally well-known entrepreneur, it is not surprising that his death last week was noted by many local publications. However, Bose Corp. is known everywhere as a provider of some of the best acoustic equipment in the world, so the passing of Amar Bose has been noted by the international press as well.
I remember being in Paris in the late 1980s, having dinner there at the apartment of some friends. They were insistent that I sit in a specially marked spot in the middle of the room to fully appreciate the symphony hall-like quality of their new sound system. They had just purchased a set of Bose speakers, which were positioned carefully to create a magical experience for whoever sat in that special seat. I did as I was told and found that my hosts were absolutely right. It was uncanny how rich and full and lifelike the sound was there, as if one were sitting in Davies Hall listening to MTT direct Mahler. It was indeed magical.
The man behind the excellence of this sound had a typical MIT CV. He was a first-generation American whose parents had fled political upheaval in their homeland. He came from an educated family. He earned his bachelors, masters, and Ph.D. at MIT in electrical engineering. He spent a year back in the Old Country doing a Fulbright and then returned to MIT to teach for the next 45 years. Basically, he spent his entire adult life at MIT. Typical.
Thursday, July 4th, 2013
A note: Since composing this blog, the terrible crash took place at SFO. This tragedy is being felt keenly in the tech industry as it is possible that some of those on board were coming to San Francisco for Semicon West. Many people at the conference may have a special connection to the injured and/or have had their travel plans radically altered while SFO is attempting to deal with the aftermath. The people at EDACafe wish to express their deep concern for everyone affected by the accident.
This is clearly a holiday week, so most people are paying more attention to the barbeque than next week’s massive Semicon West in Moscone Center, so let’s keep this pre-event note short and to the point.
It is always [somewhat] telling to see who is and who is not sponsoring conferences, and Semicon West is no exception. What can be discerned, for instance, from the fact that GlobalFoundries is a sponsor of the conference this year, but TSMC is not? That Mentor Graphics and Synopsys both have their names on the sponsor list, but Cadence does not?
Wednesday, July 3rd, 2013
Perhaps it’s an unlikely topic for a blog on a website all about EDA and IP, but making wine is the subject herein nonetheless, and the reason is simple: Long-time EDA veteran Bob Smith, Senior VP of Sales and Business Developmental at Uniquify, has been leading a double life – EDA exec by day and wine-maker extraordinaire by nights/weekends.
Smith and Joe Lazzara started Jazz Cellars winery back in 2005, and since that time have burdened friends and family with their obsession for making fine wines, now award-winning fine wines. Their operations are centered in Dogpatch, a distinctly trendy neighborhood in San Francisco just south of the ballpark that’s grown even trendier now, thanks to Dogpatch WineWorks where Jazz Cellars and other boutique vintners share the costs of doing business.
Thursday, June 27th, 2013
Atrenta VP Mike Gianfagna graciously extended an invitation to attend an event this evening in Grenoble, France. Jointly sponsored by CEA-Leti and Atrenta, Mike said the event was to be held on the CEA-Leti campus “in conjunction with Leti Innovations Days” and would “toast the progress Atrenta has made at its R&D facility in the city.”
It would have been great to have been there, as I was in Grenoble back in March 2011 when Atrenta first inaugurated its R&D center at the Micro and Nanotechnologies Innovation Center (MINATEC) in the city. The 2011 event was marked by a wonderful wine-enriched reception and a series of speakers articulating Atrenta’s vision in partnering with MINATEC. Those speakers included Atrenta CEO Ajoy Bose and STMicro’s Executive Vice President Philippe Magarshack, among others. You can see my original 2011 post below for more details.
Alternatively, if you want to know more about this evening’s reception in Grenoble, I have cut-and-pasted Mike Giafagna’s notes immediately below that he sent summarizing the event after the fact. It was not surprising to learn that Ajoy Bose spoke this evening, but to learn that Philippe Magarshack was also there, as he was in 2011, gives pause.
Wednesday, June 26th, 2013
This morning, San Francisco’s Asian Art Museum previewed their newest exhibition for the press, In the Moment: Japanese Art from the Larry Ellison Collection. It opens to the public on Friday, June 28th, and is well worth a visit.
Yes, Mr. Ellison is the fifth richest person in the world and clearly we all know he’s spent a lot of that wealth on real estate, airplanes, a variety of things that float, and most recently in reconfiguring the San Francisco waterfront in anticipation of the upcoming America’s Cup event.
What is less well known is that Ellison has also converted a portion of his wealth into art – art from Japan specifically, some of it many centuries old. It’s that collection, or a small part of it, that’s currently on display at the Asian Art Museum across the plaza from City Hall in the heart of The City.