Archive for the ‘Uncategorized’ Category
Thursday, December 12th, 2013
At a recent tech conference in Silicon Valley, I had a chat with a long-time EDA player; let’s call him Elmer. The conversation came around to Jasper Design Automation and conjectures as to what’s ahead for the company. I recounted a small compare and contrast.
At the 2008 February EDAC CEO Forecast Panel, Jasper CEO Kathryn Kranen was on stage along with Synopsys CEO Aart de Geus, Mentor CEO Wally Rhines, and then-Cadence CEO Mike Fister. During the panel discussion, Kranen criticized the Big EDA companies on the panel for their ‘all you can eat’ business strategies – the big companies providing less-than-best-in-class point tools for free to customers who purchased their anchor products, which Kranen said made it nearly impossible for the smaller companies to compete.
Thursday, December 12th, 2013
Last week, I had a chance to interview the founder of Career Girls, a YouTube channel chock-a-block with 220+ video interviews of successful women talking about how they got started in their careers, what educational background they needed for those careers, and what features and/or people in their lives helped to bring them to where they are today.
All good stuff, but then this week Mary Barra was named CEO of GM – yeah, yeah, you’ve already heard – the first woman CEO of a major American automobile manufacturer. Outgoing CEO Dan Akerson is quoted as saying, “Mary was not picked because of her gender or political correctness, [but because] Mary’s one of the most gifted executives I’ve met in my career.”
So, it’s a meritocracy after all? If that’s the case here in 2013, do we actually still need something like CareerGirls.org to encourage our daughters to be all they can be? Well, despite Detroit’s Mary Barra, and the likes of Meg Whitman, Marissa Meyer, and Sheryl Sandberg here in Silicon Valley, there are still, according to some studies, very few women anywhere near to the top in big business. And we need look no farther than EDA to prove it … again.
Tuesday, December 3rd, 2013
When it comes to high-tech, it’s not just those who hang out in Silicon Valley whose sacrifices at the Alter of Innovation must be generously funded and then widely touted. Captains of high-tech industries everywhere must spend oodles on R&D and then brag about it, year in and year out, regularly releasing their R&D budget numbers so people (particularity stockholders) can sense the true scale of the organization’s commitment to the Great Cult of Innovation.
It turns out, however, it’s easy to talk the talk, but much tougher to walk the walk.
It turns out – even though of late, companies like IBM have put up annual growth numbers in the range of 40% and Apple’s have been almost double that – over the last 40 years, actual growth rates in high-tech have been measurably less than growth rates across non-high-tech industries. And this, despite the fact that R&D budgets in high-tech have persistently been 75% bigger, as a percentage of revenue, than R&D budgets for their non-high-tech sector counterparts.
Are you following this? In other words, the ROI on R&D in high-tech – the amount of growth that has resulted from all of that R&D investment – has been shockingly low, and it’s not just because various markets for high-tech goods are saturated.
Thursday, November 21st, 2013
Mentor Graphics has just posted a very interesting white paper on their website that discusses the advantages of combining ATPG and logic BIST to produce improved test coverage: Improve Logic Test with a Hybrid ATPG/BIST Solution, by Ron Press and Vidya Neerkundar.
The paper’s a good read for several reasons. There’s a brief, but accessible explanation of both ATPG and logic BIST, and then an equally accessible explanation of the benefits of combining the two to create a hybrid test approach.
This week, I spoke with Mentor’s Steve Pateras and Gene Forte about the paper and asked why, at this late date in the development of ATPG [automatic test pattern generation] and BIST [built-in self test], the paper starts with basic explanations of these two seemingly well-established test strategies.
Thursday, November 14th, 2013
Cadence is announcing this week a new product for power integrity and signoff called Voltus, which the company says solves several problems simultaneously.
Per a phone call with Cadence Director KT Moore, one of the challenges in power signoff is that it takes a lot of time: “When designers look at analyzing power for the block, chip or package, current analysis techniques can literally take days, so designers are looking for a faster solution. What Cadence believes to be true about Voltus is that this product is 10x faster than any existing solutions available today. Because of that, we know the customers are very excited.”
“The other issue with power signoff,” Moore said, “is that it needs to be accurate. You can make a product a thousand times faster, but it’s of little value if it’s not accurate. With Voltus, however, we’re maintaining the same accuracy compared, for instance, to Spice or whatever the customer’s expectation reference is. But there’s an additional level of accuracy in Voltus that’s also important.
Thursday, November 14th, 2013
This week in Las Vegas, Dassault Systèmes hosted one of their many global confabs where customers consult with each other about the joys of using Dassault’s product lines. At this particular conference, Panasonic’s newly launched ToughPad enjoyed special focus, featuring heavily in keynotes and on the exhibition hall floor.
The 20″ ToughPad is among the largest tablets in the history of humankind, weighing in at around 6 pounds, and comes in two versions. One’s targeted at sales folks who want to haul around a huge screen for maximizing presentation punch (and for watching movies while they’re waiting at the gate). That one sells for around $5K. The other version’s a full-on workstation, good for designing stuff, repairing helicopters (virtually), and spinning things around and around in Dassault’s 3D design software until you’re dizzy with delight. This more-powerful, badasser version will set you back around $7.5K or more, but surely it’s worth the price.
Thursday, October 31st, 2013
[Editor’s Note: An abbreviated version of this article first appeared on-line on in July 2001, and again in May 2004 when Gary Smith was engaged to be married to Verisity’s Lori Kate Calise.]
Starting and ending with the Tao is pretty enigmatic stuff when, in the middle of the stream, you find a bass-toting, black-leather-clad blues musician fresh out of the Naval Academy living in a shack in the midst of Silicon Valley. That pretty much summarizes Gary Smith for those who know him. For those who don’t, to quote from an introduction to Gary I heard at a panel last year where he was acting as moderator: “If anyone in this room doesn’t know who Gary Smith is, they don’t belong in this room.”
For a number of years, Gary Smith has been the single most important prognosticator in EDA. The industry listens to Gary, at DAC and a thousand other venues over the course of the year. They bank on his annual numbers reporting on the health of the industry. They pin his EDA Landscape poster up on the wall to keep track of which companies are which in the here today/acquired tomorrow world of EDA. They take their business plans and nascent product ideas to him and hope for his blessings. They quote him. They court him. They keep him busy, and apparently he loves it – taking all of the adulation in stride with a smile and a nod, which is what you would expect from a guy who takes Eastern philosophies seriously and incorporates them into his mindset and lifestyle.
The rest of Gary’s story is as follows. However, if you believe as Gary does that less is more, you needn’t read on. Based on what you’ve read, you already know him.
Thursday, October 24th, 2013
If you are someone who does formal verification and is looking for a chance to talk over the challenges with others who do similar work, Oski Technology has something that may be of interest to you. Starting this month in Silicon Valley, the company is kicking off its Oski Decoding Formal Club. The inaugural meeting took place at the Computer History Museum on October 10th, and was lead by company CEO Vigyan Singhal.
Over lunch, he presented a 45-minute overview titled, “Using Bounded Proofs in Formal Sign-off.” Singhal noted during his talk that it’s the reality today that formal is expensive and returns “low bang for the bucks.” He insisted, however, that if there were places to learn more about how to apply formal verification, and how to build a productive formal team, the technology would be more widely applied and its destiny more quickly fulfilled as an extremely effective technique for use end-to-end throughout the design process.
Following Singhal’s presentation, the 20+ people in attendance (representing 10 companies) were each given time in a relaxed, roundtable environment to share their experiences and/or frustrations with formal. The companies included Apple, Broadcom, Cisco, HiSilicon, Memoir Systems, Microsoft, Nvidia, Palo Alto Networks, Qualcomm, and a startup. In other words, companies both big and small were represented and the resulting conversation was very interesting. It was clear as the talking stick was handed around, that some practitioners were very confident and sure of themselves, while others were relieved to know they’re not the only ones who struggle with formal.
Wednesday, October 16th, 2013
Several years ago, after a phone briefing about a new product launch, I received a call back from the PR counsel who had organized the meeting. She asked me if I had all the info I needed regarding the product and the company. I said yes, and offered a minor apology for asking too many pointed questions of the marketing manager during the interview.
She said, “Oh, that’s okay. Talking to you is like talking to Aart de Geus. It’s clear you both think you’re the smartest guy in the room.”
That comment has come to mind multiple times since then, for two reasons. One, you never really know what impression you leave with people until it comes out at some capricious moment. And two, Aart de Geus isn’t the smartest guy in the room, just because he thinks so. He’s the smartest guy in the room, because he really is the smartest guy in the room.
That’s particularly applicable today with the EDAC event celebrating the 50th Anniversary of the EDA industry about to commence this evening in Silicon Valley. Per the Consortium, a plethora of industry luminaries will be in attendance. Per this writer, none will be more luminary than Dr. de Geus. If you’re reading this, you’re probably pretty well versed in both the history of EDA and the history of Aart de Geus. Nonetheless, here’s the latter in a nutshell.
Thursday, October 10th, 2013
Given that history and innovation are being featured here in this space this week, it’s only appropriate to highlight the fact that EDAC is hosting a very interesting event related to history and innovation in Silicon Valley next week.
On Wednesday, October 16th, those who have made massive contributions to the EDA industry will be highlighted and celebrated at a black-tie optional dinner at the Computer History Museum. If you’re interested in rubbing elbows with the powerful and prolific, you should be going to this event. If you want a chance to bid at auction for lunch with today’s corporate leaders in EDA, you should be going to this event. If you think said corporate leaders make enough money to pay for your lunch, rather than vice versa, you should still be going to this event.