Archive for the ‘Uncategorized’ Category
Thursday, September 19th, 2013
Mentor Graphics has thrilled once again. This past Monday, they hosted one of their periodic Silicon Valley dinners for customers, press and analysts where they include a physicist on the menu along with a gourmet meal and lots of fine reds and whites. The physicist de jour on September 16th was Cal Tech celeb Sean Carroll, author of the best selling book, The Particle at the End of the Universe.
An excellent speaker, gifted and glib, Carroll walked his audience of 75+ through stuff they once knew but had forgotten, or never knew at all – the history of the science of particle physics, the evolution of field theory, and the importance of Geneva-based CERN and its still-wet-behind-the-ears Large Hadron Collider [LHC], which last year on July 4th validated its $9 billion+ price tag by smashing things around a bit and creating the first observable Higgs boson.
Wednesday, September 11th, 2013
Several weeks ago on a warm, sunny day in New York City, we took the subway south from mid-town Manhattan to return to the World Trade Center after a 10-year hiatus.
The last time we were there in 2003, the skies were gray, the rain intermittent, and the enormous site still cordoned off by an endless chain-link fence. With thousands of other silent tourists, we wandered way around the soggy gaping hole, crossed a covered catwalk, and were channeled into the lobby of the World Financial Center to see models of proposals for the site – a range of different commercial towers combined with various concepts of memorials that might be incorporated into the rebuilt complex.
Returning now in 2013, we did not know what to expect; we were only vaguely aware of how the place is being brought back to life. Had a stranger on the subway not told us, we would not have known that you need tickets to get into the site, that the ticket office is several blocks away from the entrance, and that you will be assigned an entry time that may be hours away. We decided to try to go anyway.
Thursday, September 5th, 2013
Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.
In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.
Fully-depleted SOI …
Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.
“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.
Wednesday, August 28th, 2013
Perfectly suited by nature to teaching, when affable Cliff Cummings steps up to conduct his Verilog course, the class is in for a treat. From the get-go, Cliff establishes a tone of respect, humor, and openness to questions of any kind. He encourages students to interrupt when they don’t understand, to stand up, sit down, resort to coffee and/or carbs, and in all ways to relax and enjoy the learning experience.
There’s something additional, however, that Cliff brings to his inspired task of teaching and that’s his decades of involvement with the Verilog language, its evolution, standards, and implementation. What Cliff Cummings doesn’t know about Verilog and SystemVerilog, isn’t worth knowing. Period.
This week, Cliff is teaching Verilog-2001 Design & Best Coding Practices in Silicon Valley – specifically, in the offices of EDA Direct – and I’ve been lucky enough to attend. Not being a Verilog expert, I approached the class with some trepidation, but found to my delight that I was not the only one among the 8 engineers in the room “new” to the language. We’re all engineers, but we’re not all Verilog designers and hence it’s a class perfectly suited to our skills, interests, and goals.
Thursday, August 15th, 2013
Kevin Steptoe is VP of Engineering at Sondrel, a global chip-design consultancy based in Reading, U.K. We spoke this morning by phone about the future of FinFETs, in particular Steptoe’s reaction to my blog posted earlier this month, FinFETs: Yes, No, Maybe.
Steptoe said there’s nothing maybe about FinFETs. They are most definitely “an absolute yes” – revolutionary and disruptive as they may be – and offer great promise for the future of chip design, manufacturing, and deployment. And he said, his enthusiasm for the technology is not just from Sondrel’s point of view, but from his own personal involvement in the industry that extends back several decades.
Per Steptoe: “As the world’s increasingly insatiable demand for mobile, tablet-based, higher frequency devices ramps up, the predominant challenges for engineers and designers translate into fears of leakage power and performance. The FinFET, in its construction, addresses these challenges and makes mobile devices dramatically more possible.
“[In fact], the control of the short-channel affect and suppression of leakage actually simplifies things, so engineers will have the opportunity to achieve much higher [transistor] density, much lower power, and similar-or-increased performance levels. We see FinFETs as a win all the way around, a no-brainer that will fully live up to what it says on the tin: With FinFETS you will design ever larger devices with an ever higher power profile.”
Wednesday, August 7th, 2013
Well, it looks like the industry has done it again, delivering good growth over a recent quarter. The Press Release issued by EDAC’s Market Statistics Service on August 6th detailed the numbers for Q1_2013: 8.1% growth overall, including 23.8% growth in Services, 20.2% growth in IP, and (a bit less glam) 2.4% growth in EDA. Interesting.
Meanwhile, Dr. Wally Rhines continues to contribute to the industry by making himself available for conversation about the MSS numbers as they are released each period, clarifying as always that his comments are on behalf of EDAC and do not reflect his role as CEO of Mentor Graphics. When I spoke by phone with Rhines earlier this week, I asked him if we can anticipate industry results for all of 2013 by looking at the Q1 numbers.
He said no, EDAC numbers do not portend the future, they only aggregate the results from the past. To know more about the future of the industry, Rhines referred me to the four visionary keynotes given at DAC by Synopsys’ Aart de Geus, Cadence’s Lip-Bu Tan, Jasper’s Kathryn Kranen and Rhines’ own talk.
Thursday, July 25th, 2013
Ed Sperling, Editorial Director for Semiconductor Manufacturing and Design Community, moderated a breakfast panel on Tuesday morning, June 4th, at DAC. Having missed the bulk of the event, I was fortunate to have a chance later to review the slides of the five speakers: Cavium Networks VP Anil Jain, GlobalFoundries VP Subramani Kengeri and Director Kelvin Low, and Synopsys VP Raymond Leung and Senior Director Bari Biswas.
Having now gone through the slide deck twice, I’ve come away with a set of conflicting messages. On the one hand, the challenges of FinFET implementation are so great there is still much to be done, and the promise of the technology is yet to be fully proven. On the other hand, the synergy between GlobalFoundries and Synopsys is so excellent the challenges associated with FinFET implementation are definitely being met. So which is the more accurate message?
Tuesday, July 16th, 2013
Sitting in beautiful Boston on a sunny morning in July, with Cambridge just across the Charles River, it is a wistful exercise to contemplate the life of Amar Bose. Given that Dr. Bose was a well-known professor at MIT and an equally well-known entrepreneur, it is not surprising that his death last week was noted by many local publications. However, Bose Corp. is known everywhere as a provider of some of the best acoustic equipment in the world, so the passing of Amar Bose has been noted by the international press as well.
I remember being in Paris in the late 1980s, having dinner there at the apartment of some friends. They were insistent that I sit in a specially marked spot in the middle of the room to fully appreciate the symphony hall-like quality of their new sound system. They had just purchased a set of Bose speakers, which were positioned carefully to create a magical experience for whoever sat in that special seat. I did as I was told and found that my hosts were absolutely right. It was uncanny how rich and full and lifelike the sound was there, as if one were sitting in Davies Hall listening to MTT direct Mahler. It was indeed magical.
The man behind the excellence of this sound had a typical MIT CV. He was a first-generation American whose parents had fled political upheaval in their homeland. He came from an educated family. He earned his bachelors, masters, and Ph.D. at MIT in electrical engineering. He spent a year back in the Old Country doing a Fulbright and then returned to MIT to teach for the next 45 years. Basically, he spent his entire adult life at MIT. Typical.
Thursday, July 4th, 2013
A note: Since composing this blog, the terrible crash took place at SFO. This tragedy is being felt keenly in the tech industry as it is possible that some of those on board were coming to San Francisco for Semicon West. Many people at the conference may have a special connection to the injured and/or have had their travel plans radically altered while SFO is attempting to deal with the aftermath. The people at EDACafe wish to express their deep concern for everyone affected by the accident.
This is clearly a holiday week, so most people are paying more attention to the barbeque than next week’s massive Semicon West in Moscone Center, so let’s keep this pre-event note short and to the point.
It is always [somewhat] telling to see who is and who is not sponsoring conferences, and Semicon West is no exception. What can be discerned, for instance, from the fact that GlobalFoundries is a sponsor of the conference this year, but TSMC is not? That Mentor Graphics and Synopsys both have their names on the sponsor list, but Cadence does not?