Thursday, April 17th, 2014
Overlooking the inky calm of Monterey Bay, the lights of tethered boats in the marina reflecting in the shimmering waters below, Wally Rhines delivered a mesmerizing after-dinner keynote on Thursday night, a gift to an intimate group of EDPS attendees assembled in the low-slung Monterey Bay Yacht Club adjacent to the municipal pier.
It was textbook Rhines: a detailed re-telling of the last 50 years of the semiconductor industry with a log-log analysis of the validity of various versions of Moore’s Law, a dizzying display of data on shrinking feature sizes, and an adamant admonition that the law is, in fact, an economic learning curve with applicability that extends beyond the narrow confines of electronics.
From there, Rhines talked at length about what constitutes a process node, the gulf between Engineering’s obsession with gate length and Marketing’s obsession with world domination, and how reality got so out of whack with message that in recent years the ITRS had to step in and put an end to a war of claim versus counter-claim. Nonetheless, per Rhines, one company’s 16nm today is another company’s 14nm, as the murky physics behind the labels obfuscates to confuse the customer and confound the competition.
But the real core of Rhines’ talk was still to come: He addressed the issue of margins, head-on, across the entire spectrum of the semiconductor food chain, one micro-segment at a time. To do this to completion required many more charts, extensive additional analysis, and a lot more time. Yet, even as the hands of the clock over the bar inched well past 9 pm, no one in the room budged, yawned, or dozed – so complete was Rhines’ mastery of the material and command of the context. It was brilliant.
Thursday, April 10th, 2014
As a journalist, you often talk to product managers of EDA companies. Sometimes, you talk to VPs, SVPs, or even EVPs. On the rare occasion, you might event speak with a CEO. This last, being more likely if it’s the CEO of a small EDA company. Of course, these days small companies in the industry are harder and harder to come by, consolidation being the current national pastime across the width and breadth of the EDA Nation.
As a journalist, however, the kind of person you rarely talk to is someone in sales. And that’s not necessarily a bad thing.
On the rare occasion when a journalist talks to an EDA sales person, it’s usually at big vendor-sponsored dinners associated with large conferences, evening events set aside to entertain press, analysts, and customers where there’s some sort of company rep assigned to sit at each table. It’s on those rare occasions that a journalist might accidentally end up sitting next to, and talking to, someone from EDA Sales – all the way through the salad, the main course, the dessert, and even through the after-dinner entertainment.
And it’s during those rare encounters at big dinners that many journalists realize that the EDA industry they thought they knew, is a completely different kettle of fish, a completely different entity, from the one where EDA sales people live and work.
EDA Sales occupies a completely different EDA Nation from the one journalists hear about from EDA product managers, executives, or marcom specialists who busily spin narratives about the company specifically for the benefit of the press and the endearing little stories they write.
Thursday, April 3rd, 2014
There are lots of clever ways to tell you why it’s worth your while to attend EDPS in Monterey on April 17th and 18th. It’s less noisy than DAC, less vendor-specific than CDNLive, SNUG or U2U; less crowded than ISSCC; has fewer presentations than DVCon; and boasts no co-located events to confuse your schedule like at ISQED. But that doesn’t tell you why EDPS is worthwhile. It’s the list of speakers and the setting that should convince you to carve out some time on that Thursday and Friday to run down to Monterey – a scenic hour’s drive from Silicon Valley – to attend the 21st annual Electronic Design Process Symposium.
On Thursday, Wally Rhines is giving the keynote after dinner; during the day, Gary Smith’s moderating a session on design flow challenges that includes Frank Schirrmeister, John Swan, Gene Matter, Jim Kenney, and Naresh Sehgal; Sehgal’s leading a session on pre-silicon software development platforms that includes Camille Kokozaki, Shantanu Ganguly, Kumaraswamy Namburu, Schirrmeister, and Vicki Mitchell; Herb Reiter’s moderating a session on FinFETs, 3D-ICs, and FDSOI, that includes Jamil Kawa and Paul McLellan; and the kick-off keynote on Thursday morning will be given by Intel’s Chris Lawless talking about pre-silicon platforms for software development.
On Friday, Dan Nenni’s leading a whole day on IP that includes Martin Lund, Patrick Soheili, Warren Savage, Kurt Shuler, Lluis Paris, Carey Robertson, and Bernard Murphy. Finally, Aparna Dey is General Chair for EDPS. All together, that’s 24 people and a robust ecosystem of knowledge and experience comprising this year’s EDPS program.
Thursday, March 27th, 2014
The last time I had a lengthy conversation with Dr. Andreas Kuehlmann, he was director of Cadence Research Labs, housed in an off-campus office building just across the street from U.C. Berkeley. I spent an hour touring the lab, located on several floors there, with Kuehlmann as my tour guide.
First launched in 1993, by 2007 the Cadence lab was enjoying incredible new facilities when I visited, heavily kitted out with shiny work stations, high-end desks, fancy seating, gleaming conference rooms, and the usual array of tech-toys one expected to be on-site to entertain the young fanciful ones whose creativity apparently relied on having their work stations and their play stations positioned in close proximity
At the time, Mike Fister was King at Cadence. His reign, although now thoroughly besmirched by history, included in the plus column the company’s ongoing funding and encouragement of their Berkeley-based BlueSky TechLab/PlayPen.
During my visit in December 2007, my tour guide explained in great detail how Fister had been there several days before and had again reassured Kuehlmann that he had at his disposal all of Cadence’s resources: Kuehlmann’s job was not to worry about funding, only to worry about the rate at which his feisty group of wunderkinds were turning out innovative ideas that could be embraced by the mainline Cadence organization and brought to market.
Wow, what a gig, I probably said at the time, and Kuehlmann probably agreed: Cool digs just a few quick steps away from Cal’s engineering brain-trust, cool young folks soldiering away all around him, and a way cool corner office for the lab’s director that looked straight out to the Golden Gate Bridge. What wasn’t to like about that set-up?
Wednesday, March 26th, 2014
If ever there was a need for additional help in design, now is the time. As the industry marches down, node after node, the problems ramp up, node after node.
After my conversation with Mentor’s Joe Sawicki several weeks ago about all of the pros/cons of moving to the next node, it was good then to speak with Sage-DA CEO Coby Zelnik about how his company’s tools are designed to help solve the single most ferocious problem that arises once designers in the trenches are ordered to make that move – the explosion in number and complexity of design rules.
Given that you all know how design rules work, can you quote chapter and verse about how the numbers of rule operations increase in the DRC Manual with each progressive node? Zelnik included a slide in his presentation last week that laid out the nightmare. At 65 nanometers, it’s 3000 rules; at 40 nanometers, it’s 4000 rules; At 28, it’s 8000. But at 20 and 16, the number stands at a staggering 16,000. The sheer magnitude of those numbers is what made the conversation last week with Zelnik so interesting.
Monday, March 24th, 2014
March 24th, 6:01 AM – Later this morning at Silicon Valley SNUG, the CEO of Synopsys will be presenting a keynote that will most likely dwell on the newest major tool release from his company: IC Compiler II.
Synopsys notified the press several weeks ago that the announcement would be made this morning, but we would only be blessed with a pre-briefing if we promised to honor the embargo. Undoubtedly most agreed to these most conventional of terms. However, either ESNUG was never asked, or simply learned details of the launch through more creative channels; a preliminary description and critique of ICC II were published there last Thursday for all to see.
When I asked Synopsys last Friday morning if the ESNUG post made their embargo invalid, it was clear I had touched a nerve in their organization. They were absolutely adamant that the embargo was still valid, and if I refused to promise to honor it, not only would I not receive my pre-briefing later that day, I would never receive another pre-briefing from Synopsys going forward. Ever.
Okay then, I’ve honored the embargo. I’ve also used the information published on ESNUG last Thursday afternoon to inform my interview with Synopsys last Friday afternoon. Speaking for Synopsys on my March 21st conference call with the company was Sanjay Bali, Director of Product Marketing. Numerous PR people were also on the call. Here’s an abbreviated report on how the interview went.
Friday, March 21st, 2014
It’s Friday afternoon and spring is busting out all over, so why would anyone want to sit on a conference call and talk about EDA? Well, if you were Ravi Subramanian, President and CEO of Berkeley Design Automation, you would. The company he leads has just been sold to Mentor Graphics and today’s his day to celebrate the feat with the press.
I spoke with Ravi for 20 minutes this afternoon and remembered straightaway why he is the real thing. Well spoken, fully informed, and completely disciplined in his presentation, still his extreme delight with the acquisition was in full view as he patiently fielded my questions.
Tuesday, March 18th, 2014
Agnisys exhibited at DVCon several weeks ago in Silicon Valley, but within the time constraints of the show I didn’t have a chance to talk with them. Fortunately, that was remedied at 9 am this morning – 9:30 pm in Noida – during a phone call with company CEO Anupam Bakshi, who was visiting his team in India at the time of our conversation.
Prior to his involvement with Agnisys, Bakshi served at Avid Technology, PictureTel, Blackstone Consulting Group, Cadence, and Gateway Design Automation.
WWJD – Let’s start with the elevator pitch. In 25 words or less, when did the company start and what do you do?
Bakshi – We started 6 or 7 years ago and are Massachusetts-based, although a lot of our development is done in Noida. Our products, called IDesignSpec, focus on the area that the big EDA companies don’t, providing an executable specification tool for chip design.
Thursday, March 13th, 2014
The following conversation with Joe Sawicki, VP/GM of Mentor Graphics’ Design-to-Silicon Division, looks at the complexities of deciding if and when a company should move down to the next process node. The interview was inspired by an upcoming panel at DAC, Designing on advanced process nodes: How many respins should you plan for?
Sawicki is an acknowledged expert in design and manufacturing, and “responsible for Mentor’s design-to-silicon products, including the Calibre physical verification and DFM platform, and the Tessent design-for-test product line.” I spoke to him by phone this week while he was traveling in Japan on business.
Wednesday, March 12th, 2014
In the spirit of full disclosure, Cadence paid for lunch yesterday for the Press Corps attending CDNLive 2014. We had a scrumptious gourmet meal at Tosca in the lobby of the Hyatt Regency before returning to the Santa Clara Convention Center next door to have an hour-long “one-on-one” with Cadence CEO Lip-Bu Tan. In truth, it was actually an hour-long “twenty-on-one” with CEO Tan, because all of the usual suspects EDA Press Corps was in the room throwing softball lobbing questions at Tan.
Over the course of the hour, we learned that CEO Tan has a host of different investment partners – sorry, didn’t write down the names – involved in his various VC-funded ventures that span everything from GoPro [the trendy wearable camera enterprise out of Half Moon Bay] to a fabless startup that he said can tape-out a design at 16 nanometers for a scant $15 million, rather than the usual $150 million being lamented today in the global press. [In fact, Tan mentioned so many ventures he’s involved with, it begs the question: How does he have time to run Cadence?]
We learned that CEO Tan is very excited about all of the technologies involved in the semiconductor design/supply chain, that he believes it’s a great time to be a player in the industry, and that Cadence is innovating rapidly on multiple fronts simultaneously. And if/whenever Tan senses that they’re slowing down in any particular area, he pushes Cadence Engineering to move forward even faster.