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Advanced node Re-spins: Be very afraid (maybe)

Tuesday, June 10th, 2014

 

UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’

In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.

Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”

It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.

Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.

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DAC 2014: Algorithms, Adjacencies, Animosities, World Peace

Thursday, June 5th, 2014

 

The June breezes were intense in San Francisco this week. The fog was swirling out at the Great Highway, and making itself known across town amidst the flags flying sharply over Moscone Center. The Electronic Design Automation and IP communities were out in force in and around South Hall, while thousands of edgy app developers were playing out their own dramas across the street and down the block in and around West Hall where Apple was holding court at the same time. Fourth and Howard was awash all week in hordes and gaggles of the people who are shaping the future of the world.

Algorithms – Perhaps as never before, algorithms were the number one topic at DAC this year, and in so many different shapes and sizes. Algorithms for high-level synthesis, algorithms for creating models, algorithms for translating physical data into guidelines for design, algorithms for translating assertions into verification metrics for more orderly validations, algorithms for encrypting and decoding, algorithms for compression and decompression, algorithms for converting approximate computational output into exactitude, algorithms for hearing, seeing, and even believing. In San Francisco this week at DAC, it was algorithms all the way down, everywhere you looked.

Adjacencies – The Design Automation Conference is all about ideas, and this year the principle idea was change. The Executive Committee re-shuffled the long-standing deck of cards that’s represented the most important topics at DAC over the last 50 years and came up instead with a whole new set of talking points.

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Phoenix Rising: Gary Smith at DAC

Thursday, May 29th, 2014

 

Like a phoenix rising from too-early reports of a reduced participation in life, the legendary Gary Smith has created a schedule of appearances at the 51st Design Automation Conference in San Francisco that would fell a man half his age. Every time you turn around at Moscone Center next week, or the Intercontinental Hotel before that, you’ll be face-to-face with events featuring the Guru Extraordinaire of EDA.

Sunday evening from 5:00 pm to 5:30 pm, Gary will yet again ring the opening bell at DAC, this year in Ballroom A of the Intercontinental Hotel across the street from Moscone. I’m putting good money on a bet that Gary will be on stage there in his best Tropical Whites, accompanied by slides, predictions, and previews of the Next Epoch in EDA and his Pavilion Panel the next day.

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Marie Pistilli: A conversation with DAC Co-founder

Thursday, May 22nd, 2014

 

Thanks to Nanette Collins, long-time EDA PR consul, we have a chance this week to catch up with Marie Pistilli. Marie co-founded DAC with her husband Pat in 1964.

Although Marie and Pat Pistilli have been fixtures at the conference they founded 51 years ago, they will not be in San Francisco this year. Pat’s recovering from surgery and the doctors have ordered him to stay home.

I can’t imagine not having the Pistilli’s at DAC, so I was very happy that Nanette was able to speak with Marie. They spoke by phone on May 19th.

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OneSpin: A must see at DAC

Wednesday, May 14th, 2014

 

There are three reasons you should visit OneSpin at DAC in San Francisco. First, they’re a German company, albeit with a group in California, so it’s great to chat with the German contingent while they’re in town; second, it’s been 10 years since they were spun out of Infineon, so they have that much experience selling verification tools into some of the largest semis in the world; and third, Dave Kelf heads up marketing for the company and any conversation with Dave’s going to leave you better informed and happy to be working in the industry. He’s the ultimate optimist.

I spoke by phone recently with Dave. It was morning in Silicon Valley and late afternoon in the U.K. as he described a new tool recently released by OneSpin that’s useful for evaluating verification coverage.

Dave said, “OneSpin’s been working on this for a while with customers. It was actually a customer who said to us: Look, you’ve got this great coverage engine. Why don’t you release it as a separate tool, because it could be very beneficial.

“So we looked at our coverage engine, added some features, made it useful to a number of different companies, and released it as Quantify. The response has been great. It’s really started to transform the environment for our customers, a group of very high-end companies.”

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Power & Beauty: Defining DAC in the 21st Century

Wednesday, May 7th, 2014

 

In the same week that glamorous images from the Met Gala in New York City and the White House Correspondents Dinner in Washington, D.C., remind us that power and beauty are closely linked, how appropriate to hear that CMU’s Dr. Diana Marculescu has been named the 2014 recipient of the Marie R. Pistilli Award by the DAC committee for Women in Electronic Design.

With a PhD in Computer Engineering, and over a decade of commendations from the NSF, ACM, IEEE, ASPDAC, ICCD, ISQED, and the Carnegie Institute of Technology, Dr. Marculescu is both powerful and beautiful. She is a marvelous role model for both young women and men who want to lead lives of great intellectual vigor that are also rich with aesthetics and joy.

Prof. Marculescu is a bright, engaging technology leader and educator, has served or is serving as graduate adviser to over 20 masters and doctoral students at CMU pursuing research into CAD tools for energy, variability and reliability-aware computing, and CAD for non-silicon systems, has published over 100 papers, garnering 3 Best Paper Awards along the way, is an expert in networks and adaptive distributed systems, and is as delightful an individual as you could ever hope to meet, the embodiment of grace and charm.

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May Day: EDA in Moscow

Thursday, May 1st, 2014

 

A friend likes to spend hours on Sundays reading the New York Times cover to cover. Pointing to an article from last weekend’s edition, he exclaimed, “This Putin guy is a real piece of work! He’s a total dictator and worse, thinks he can win the world war he’s about to unleash!”

“Stay calm and carry on,” I said soothingly. “It’s a global economy these days and he will succumb to the pressures of maintaining a steady environment for international trade.”

“Yeah?” the friend scoffed. “And you call yourself a student of history? You don’t think there was a global economy in 1939?”

“Look,” I said. “Seriously. The EDA industry is in Moscow. Do you think they’d be playing in an environment that’s spiraling out of control?”

“Yeah?” he retorted. “The world, starting with Putin, doesn’t care about your precious EDA. And besides, who says EDA’s in Moscow?”

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ProPlus’ CTO: Intelligence in Design Personified

Thursday, April 24th, 2014

 

Talking to ProPlus Design Solutions requires a long view of history over at least the last 20 years in EDA. In 1993, BTA, an EDA company focused on device model extraction and SPICE simulation, was founded with U.C. Berkeley’s Dr. Chenming Hu as Chairman of the Board. In 1999, BTA merged with Ultima, and became Celestry in 2001.

Finally, in 2003, the combined companies were acquired by Cadence Design Systems. Then in 2007, a new company called ProPlus was spun out of Cadence to support the original BSIMProPlus device modeling platform with roots going back to BTA/Celestry.

Current ProPlus CTO Bruce McGaughy earned his PhD at Cal with Chenming Hu as his advisor, served at both BTA and Celestry, and worked at Cadence, before joining ProPlus 6 years ago. I had a chance to talk with Dr. McGaughy in person last month in Silicon Valley. Our conversation covered a range of topics.

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M&A: It’s Jasper to Cadence, at last …

Monday, April 21st, 2014

 

In the moments prior to Cadence’s quarterly earnings call this afternoon, the company released news of the acquisition of Jasper Design Automation for $170 million, less $24 million in cash, and a small tremor rippled out across the EDA Nation.

Paraphrasing Cadence CEO Lip-Bu Tan in the early minutes of his 5pm ET earnings call: We are very pleased to announce a definitive agreement to acquire Jasper Design Automation. This will help us to further meet our customers’ needs for more advanced verification solutions, particularly today as verification now represents 70% of the cost of SoC development. Together, Cadence and Jasper can move forward, offering the strong formal verification solutions leading customers need. In addition, Cadence is also very pleased to be bringing on board the strong team at Jasper, a team with excellent real-world experience.

All good stuff, yes? So why any tremors in our beloved little EDA Nation?

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Rhines at EDPS: masterful marine mise-en-scene

Thursday, April 17th, 2014

 

Overlooking the inky calm of Monterey Bay, the lights of tethered boats in the marina reflecting in the shimmering waters below, Wally Rhines delivered a mesmerizing after-dinner keynote on Thursday night, a gift to an intimate group of EDPS attendees assembled in the low-slung Monterey Bay Yacht Club adjacent to the municipal pier.

It was textbook Rhines: a detailed re-telling of the last 50 years of the semiconductor industry with a log-log analysis of the validity of various versions of Moore’s Law, a dizzying display of data on shrinking feature sizes, and an adamant admonition that the law is, in fact, an economic learning curve with applicability that extends beyond the narrow confines of electronics.

From there, Rhines talked at length about what constitutes a process node, the gulf between Engineering’s obsession with gate length and Marketing’s obsession with world domination, and how reality got so out of whack with message that in recent years the ITRS had to step in and put an end to a war of claim versus counter-claim. Nonetheless, per Rhines, one company’s 16nm today is another company’s 14nm, as the murky physics behind the labels obfuscates to confuse the customer and confound the competition.

But the real core of Rhines’ talk was still to come: He addressed the issue of margins, head-on, across the entire spectrum of the semiconductor food chain, one micro-segment at a time. To do this to completion required many more charts, extensive additional analysis, and a lot more time. Yet, even as the hands of the clock over the bar inched well past 9 pm, no one in the room budged, yawned, or dozed – so complete was Rhines’ mastery of the material and command of the context. It was brilliant.

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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