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 What Would Joe Do?

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EDA in Moscow: Business as Usual, the Glue that Binds

Thursday, August 7th, 2014

 

Ten years ago, numerous hardworking folks in EDAC struggled long and tenaciously to get EDA software removed from a host of restricted-overseas-commerce lists. For those efforts several members of the EDAC community were honored, while sighs of relief were breathed that the industry would not be foolishly restricted by the U.S. Government from exporting their agnostic-to-end-use software.

After all, why would electronic design software have anything to do with communications, avionics, surveillance, ground-based mechanized weaponry, or surface-to-air missile guidance systems, let alone a host of other electronic junk? ‘Just because we made it, doesn’t mean we want it to be used by the bad guys for evil purposes,’ the EDA industry said. And added, ‘Heck, we just produce the stuff. We’re not responsible for how it’s used.’

Of course, that’s not to say that restrictions and guidelines for international commerce have not applied to both EDA and IP. In September of last year, I attended an evening seminar hosted by EDAC that, thanks to the articulate intelligence of Cadence Group Director for Export Compliance and Government Relations Larry Disenhof, outlined in detail the complexities and convoluted guidelines that business folks in the United States must adhere to if they want to stay legal and in business when participating in overseas trade.

It all seemed highly confusing and fraught with the dangers of inadvertently operating outside the lines of what the U.S. Government considered appropriate behavior. Nonetheless, Disenhof offered hope that if companies paid close, close attention to the shifting sands of international relations – pretty much on a daily basis – they would be okay when it comes to obeying the law.

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Invionics: Optimism leads to Innovation

Tuesday, July 29th, 2014

 

There are two ways you could have talked to the young Vancouver-based company Invionics in June. Make your way to British Columbia, or seek them out in the Verific booth at DAC in San Francisco. The second option is how I got to chat with Invionics CEO Brad Quinton, and although our conversation amidst the organized chaos of DAC was brief, it left the impression of a company with a bold future ahead.

Per their website, the company’s products include “design tools, hardware IP and EDA development platforms.” However, Invionics also provides “experienced contract R&D to extend our products and IP, [which enables our] customers to quickly implement key functionality and gain competitive advantage for their products.”

In other words, Invionics is my favorite kind of company: A product company that’s also a services company. Of course, this is my evaluation and not necessarily theirs. Nonetheless, it was completely refreshing to talk to somebody at DAC who seems to look at things with a new perspective, an optimistic perspective that’s all about charting a new path going forward.

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Rhines: EDAC’s Numbers as The World Turns

Thursday, July 17th, 2014

 

Once again EDAC’s Market Statistics Service has released quarterly results for the EDA and IP industries, and once again Mentor Graphics CEO Wally Rhines has taken time to debrief the press on the numbers. When we spoke by phone on July 15th, Rhines started with a qualitative eval of the financial situation in Q1_2014, and moved from there to answer several longer-range questions about autos and today’s troubled world.

“The first quarter of 2014 was good for the industry, but not great,” he said. “With overall growth of 4.6 percent, year over year, it was a good quarter with the highlight being logic design was up a solid 6.6 percent. Other than that, there was not a lot else [remarkable in EDA].”

“Steady, but not glamorous, for Q1?” I asked.

Rhines said, “Yes, steady as she goes in EDA. The IP business, however, was up strongly in Q1, driven up by results from the non-reporting companies, not members of EDAC. We collect public info from non-reporting IP companies such as ARM, Imagination Technologies, MIPS, Rambus [and Synopsys], and we can see overall that the IP business [exhibited] 10-percent growth, quarter over quarter, Q1_2013 to Q1_2014.”

He added, “The bigger trend [visible in] the current MSS report is that all of the world is showing strong [sales], except Japan which is very weak, down 19 percent in contrast to Asia Pacific, which is up 13.5 percent.

“You should also note that North America and Europe are quite strong, up 7 percent or more.  Japan is well below those regions as well. Japan used to be a big part of the total [numbers for the industry], substantially larger than the Asia Pacific Region, but now the Pac Rim is twice the size of the Japanese market.”

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Silicon Cloud: Architecting the Future of Design

Wednesday, July 16th, 2014

 

Despite its ethereal-sounding name, Silicon Cloud International is a company grounded in the reality of chip design, particularly for an important international demographic, professors and students. Mojy Chian is CEO of the Singapore-based SCI. We spoke recently by phone.

Chian started by defining the cloud. “The concept of the cloud is straightforward. It means remote computing, so if you are not using your local machine, you are using the cloud. There are a lot of applications in the cloud, including eCommerce, Facebook, cloud storage, and remote collaboration based in the cloud.

“Certainly, usage of the cloud has taken off in recent years, but remember there are several different types of clouds. In contrast to private cloud computing, public cloud computing means accessing machines [owned by other companies such as Amazon], where you can actually go and use their machines.”

Our conversation being specific to chip design, I asked Chian to comment on widespread industry concerns regarding security when working in the public cloud. Companies are oft-times reluctant to compute and/or store their designs in the public cloud for fear of losing their precious data to hackers and pirates.

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DAC 2014: Advanced nodes and going back in time for a solution

Thursday, June 12th, 2014

 

In response to my blog this week about the June 5th panel at DAC, “Advanced Node Re-spins: Be Very afraid (maybe)“, Bill Martin, President/VP of Engineering at E-System Design, sent the following comments.

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For 15 years, I was on the same process-node-jumping bandwagon. Always looking for that next node to help solve cost, performance, area and speed that might help with the overall schedule. Even in these older (larger) processes, each new process required 2x the resources (people, time, machines, etc.) to achieve tape out.

Fortunately, I was happily ‘stuck’ using VLSI Technology’s foundries, processing and wafers. Although we were not perfect, we did learn quickly to hone processes, models, design flows, etc., to minimize rework. But that world I knew was prior to the ASIC dis-aggregation that has taken place over the past 2 decades, and because there are pros and cons to that dis-aggregation, your summary of Thursday afternoon’s DAC panel brought back some pleasant memories, as well as nightmares. Clearly we need a new mindset!

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Advanced node Re-spins: Be very afraid (maybe)

Tuesday, June 10th, 2014

 

UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’

In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.

Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”

It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.

Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.

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DAC 2014: Algorithms, Adjacencies, Animosities, World Peace

Thursday, June 5th, 2014

 

The June breezes were intense in San Francisco this week. The fog was swirling out at the Great Highway, and making itself known across town amidst the flags flying sharply over Moscone Center. The Electronic Design Automation and IP communities were out in force in and around South Hall, while thousands of edgy app developers were playing out their own dramas across the street and down the block in and around West Hall where Apple was holding court at the same time. Fourth and Howard was awash all week in hordes and gaggles of the people who are shaping the future of the world.

Algorithms – Perhaps as never before, algorithms were the number one topic at DAC this year, and in so many different shapes and sizes. Algorithms for high-level synthesis, algorithms for creating models, algorithms for translating physical data into guidelines for design, algorithms for translating assertions into verification metrics for more orderly validations, algorithms for encrypting and decoding, algorithms for compression and decompression, algorithms for converting approximate computational output into exactitude, algorithms for hearing, seeing, and even believing. In San Francisco this week at DAC, it was algorithms all the way down, everywhere you looked.

Adjacencies – The Design Automation Conference is all about ideas, and this year the principle idea was change. The Executive Committee re-shuffled the long-standing deck of cards that’s represented the most important topics at DAC over the last 50 years and came up instead with a whole new set of talking points.

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Phoenix Rising: Gary Smith at DAC

Thursday, May 29th, 2014

 

Like a phoenix rising from too-early reports of a reduced participation in life, the legendary Gary Smith has created a schedule of appearances at the 51st Design Automation Conference in San Francisco that would fell a man half his age. Every time you turn around at Moscone Center next week, or the Intercontinental Hotel before that, you’ll be face-to-face with events featuring the Guru Extraordinaire of EDA.

Sunday evening from 5:00 pm to 5:30 pm, Gary will yet again ring the opening bell at DAC, this year in Ballroom A of the Intercontinental Hotel across the street from Moscone. I’m putting good money on a bet that Gary will be on stage there in his best Tropical Whites, accompanied by slides, predictions, and previews of the Next Epoch in EDA and his Pavilion Panel the next day.

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Marie Pistilli: A conversation with DAC Co-founder

Thursday, May 22nd, 2014

 

Thanks to Nanette Collins, long-time EDA PR consul, we have a chance this week to catch up with Marie Pistilli. Marie co-founded DAC with her husband Pat in 1964.

Although Marie and Pat Pistilli have been fixtures at the conference they founded 51 years ago, they will not be in San Francisco this year. Pat’s recovering from surgery and the doctors have ordered him to stay home.

I can’t imagine not having the Pistilli’s at DAC, so I was very happy that Nanette was able to speak with Marie. They spoke by phone on May 19th.

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OneSpin: A must see at DAC

Wednesday, May 14th, 2014

 

There are three reasons you should visit OneSpin at DAC in San Francisco. First, they’re a German company, albeit with a group in California, so it’s great to chat with the German contingent while they’re in town; second, it’s been 10 years since they were spun out of Infineon, so they have that much experience selling verification tools into some of the largest semis in the world; and third, Dave Kelf heads up marketing for the company and any conversation with Dave’s going to leave you better informed and happy to be working in the industry. He’s the ultimate optimist.

I spoke by phone recently with Dave. It was morning in Silicon Valley and late afternoon in the U.K. as he described a new tool recently released by OneSpin that’s useful for evaluating verification coverage.

Dave said, “OneSpin’s been working on this for a while with customers. It was actually a customer who said to us: Look, you’ve got this great coverage engine. Why don’t you release it as a separate tool, because it could be very beneficial.

“So we looked at our coverage engine, added some features, made it useful to a number of different companies, and released it as Quantify. The response has been great. It’s really started to transform the environment for our customers, a group of very high-end companies.”

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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