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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

ANSYS: Big Challenges attract Best Engineers

 
September 28th, 2017 by Peggy Aycinena


Vic Kulkarni is well-known in the EDA community
as co-Founder, CEO and President of Sequence Design from 1995 until the company merged with Apache in 2009, which in turn was acquired by ANSYS in 2011. Kulkarni is now VP and Chief Strategist in the Office of CTO for the Semiconductor Business Unit at ANSYS.

There is little Kulkarni has not seen in his 30+ years in Silicon Valley. Although our conversation here mostly highlights current successes at ANSYS, it’s clear he continues to be wildly enthused about the broader promises of technology and the exciting efforts underway to create tools and strategies to bring those promises to fruition. Vik Kulkarni’s enthusiasm is the kind of thing that continues to make this industry so vibrant, and makes careers herein appealing for the next generation of engineers.

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WWJD: How are things going with the company?

Vic Kulkarni: We are, of course, part of the semiconductor unit within ANSYS. We have a very exciting customer base, which is increasing, and our headcount is increasing. Things are going very well.

WWJD: Any recent announcements?

Vic Kulkarni: Yes, we announced a partnership for the first time ever with Synopsys, an interactive collaboration between our two companies, not just a hand-off, but a collaboration in true design optimization. Synopsys will now use ANSYS RedHawk as part of their IC Compiler II. [See press release below.]

It’s a very exciting announcement, with both companies now working together for the next generation of technology.

WWJD: How are we doing with Moore’s Law, the slowing or imminent death?

Vic Kulkarni: I see a slightly different picture, one contrary to what most people say. There is tremendous growth today with what people are doing with Moore’s Law, and there is also ‘More than Moore’.

We have been looking at 14-to-7 nanometers, and now at 5 nanometers. With drones, VR, AR, unlimited opportunities for IoT applications and industrial reliability, Moore’s Law continues to drive feature sizes and complexity. We’ve seen 23 papers published recently by our customers, talking about these projects.

There are lots of opportunities here, among the most interesting: Nvidia has been talking about their 21 billion transistor GPU chip that’s almost 1.8 centimeters on the side. It’s the largest chip we’ve ever seen in terms of complexity and in terms of managing so much data in the design. ANSYS has been very involved with Nvidia [in developing the chip].

And there’s ‘More than Moore’, MTM, in the chip-package system that’s not just about complexity on the chip, but also the 3D IC, stacked die, integrated packages, and wafer-on-wafer packages from TSMC.

These are examples of how we help our customers with Moore’s Law and ‘More than Moore’. There are many great challenges.

WWJD: Name a couple of those challenges.

Vic Kulkarni: From the end-customer point of view, things like automotive, there are very important challenges area like connectivity and autonomous driving.

For things like advanced mobility, since [my time] at Sequence, then Apache and now ANSYS, I have seen many customers around the world with very challenging problems. Among them, the 5G networks will be the most interesting and the most disruptive in terms of experience for the consumer.

One example: Upcoming for the 2020 Olympics, each athlete, each gymnast, etc., will be wearing a full video camera on their head or body for continuous streaming [of their experiences]. The networks will gather all of that real-time video for translation to 5G wireless networks, a real challenge that will require zero latency.

Again, how do we meet these challenges? It’s exactly these kinds of questions that really excite us, these issues of multi-physics and multi-scale that get me fully energized.

WWJD: Sounds a lot like: Buckle your seat belts, it’s going to be an exciting ride.

Vic Kulkarni: Yes, and looking again at the Nvidia chip with 21 billion transistors. It required almost 1 billion models, capacitance models, device models, and billions of geometries – and was accomplished using our Big Data Analytics platform.

When you look at the process of design, increasingly we have been working in silos, but when chips have billions of transistors, those days are gone forever. Now when a designer makes a decision about power analysis, place and route, timing analysis, it’s [all related].

A voltage drop can cause clock failures, timing failures, introduce jitter features. You try to do timing closure, but there are so many variations, so many interesting effects and Gaussian distributions within each state.

All of these issues are related, and demand that you use just one data base, and one way of looking at things. And this is where we have been focusing our efforts, on our SeaScape big data architecture for design.

To use it, you essentially just need a standard machine farm and you can look at timing, power, simulation, packaging — all those parameters can be imported into this big data architecture. It really is the next generation of design, built to benefit the customer.

WWJD: Certainly these challenges offers exciting opportunities for young people coming into the industry.

Vic Kulkarni: Yes, we are seeing that happen as we speak. And it answers the question about how we attract the next generation of engineers.

The company supports education, and I actually meet with a lot of new graduates. I tell them they must think about system design, not chip design alone: How to connect the dots between designing the chip and designing the whole phone, about industrial IoT, the connected home.

They are very excited about these opportunities. In fact, young people today are tired of web-based and consumer applications. Young engineers in China, India, Thailand, Vietnam – they are going back to the old-fashioned concept of actually creating products.

And they are interested in machine learning. We are building tools [to apply machine learning] to system design. [In some areas], we are now 95-percent close to the quality of human decision-making in design, and we will keep refining the training data sets. The more you have, the better the results. It’s about supervised learning versus unsupervised learning.

And that is where I believe we can attract the best new talent, because we are solving the most interesting problems, not just offering another Spice simulation problem, or place and route tool. We are working on problems like: How do you create the next augmented reality?

We see the world very differently frankly, thanks to ANSYS. The kinds of customers we are seeing, and the kinds of things they are doing with our simulation process are amazing – and that is how we attract the next generation of engineers.

WWJD: Is DAC a venue for showcasing the opportunities for young engineers?

Vik Kulkarni: Not to criticize the committee, but DAC should not be located-based. That focus is too narrow there. To me, it has no meaning.

DAC should not focus so much on location being important, as opposed to focusing on knowledge as important. It should be an online, world-wide conference. And because it costs so much for engineers to travel, we should create a site license for online viewing.

Consider that there are over 1200 startups in China today, but not more than 30 of them were in Austin for DAC this year. There are literally thousands and thousands of inquiring minds in Asia, thousands of engineers doing everything from chip design to customer software.

Also, there should be technical challenges [presented] at DAC. In San Francisco next year, let’s forget the traditional parties. Instead, there should be hack-a-thon party. Let’s have a party where attendees create, for instance, an ARM-based CPU-based design in 2 hours. They could crank out a brand new application during the evening.

Things like this are what Facebook and Apple have at their user events. In our own company we have hired some very smart interns, and I know these kinds of events would stimulate them.

WWJD: What do you get out of the ESD Alliance?

Vic Kulkarni: I have always enjoyed the meetings. This is the kind of alliance that brings companies like Synopsys and Ansys together in a classic example of what can be done, working together to solve challenges. The Alliance [highlights] problems we should all work together to solve. Truly 1 plus 1 equals more like 4 or 5.

For instance, I really enjoyed the CEO panel this spring. The things that Aart de Geus, Wally Rhines and Lip-Bu Tan all talked about   – the system market soon to be in excess of $2 trillion –really stuck in my mind. Why can’t the EDA industry get at least 2 percent of that $2 trillion?

This will only be possible if we expand our horizons, if we harness multi-physics, multi-domains, multi-scaling. The transistors are in nanometers, the chips in millimeters, the packages in centimeters. Together we should [be able to] harness this scaling,

And both the TSMC and ARM ecosystems can help us with this.

ARM, for instance, is changing the world. It’s no longer just an IP company. They are talking about the whole thing along with their partners — cybersecurity, how to solve the next-generation educational problems, what kinds of applications we can create.

WWJD: Do you have any funny stories from your career in EDA?

Vic Kulkarni: [Laughing] Well, there are those fun parties at DAC where people are dancing like crazy. You see the wierdist things, all these nerds dancing away. Although, I am learning some Bollywood moves, so this year I decided to introduce them there.

WWJD: You were introducing Bollywood moves at the DAC party?

Vic Kulkarni: [Laughing] Yes, some of our colleagues thought we should liven things up, so four or five of us decided that we needed Bollywood at the Cadence party. It was a big hit!


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The Bio …

Vic Kulkarni is Vice President and Chief Strategist, Office of CTO, Semiconductor Business Unit, ANSYS, San Jose. CA. Kulkarni is responsible for steering the business, technology and product strategy along with the leadership team at Semiconductor Business Unit, connecting the dots from chip-package-system design software solutions with ANSYS multi-physics simulation technology, Big Data Elastic Compute Platform SeaScape and machine learning. These tools address challenges faced by several verticals, ranging from ADAS, Advanced Mobile, Data Centers, Health Care, Industrial to Smart & Connected Cities.

Prior to merging with Apache in 2009 and subsequently with ANSYS, Kulkarni was a co-founder, President and CEO of Sequence Design. He was named Entrepreneur of the Month by SiliconIndia magazine and secured Sequence a spot in Reed Electronics “50 Electronics Companies to Watch”. “Global 101- IIT India’s Intellectual Treasures” publication listed him as one of the thought leaders.

Kulkarni has been featured in several publications worldwide and has participated in several industry forums and panels. He has held engineering and various senior management positions in a number of leading semiconductor and EDA companies in the Silicon Valley for over 30 years.

Vic has a MSEE in Solid State Electronics from University of Cincinnati. In 2007 the University honored him with the “Distinguished Alumnus Award. He has a B. Tech in EE from IIT Bombay.


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The Press Release …

June 19, 2017 – ANSYS and Synopsys will enable customers to accelerate the next generation of high-performance computing, mobile and automotive products thanks to a new partnership that will tightly integrate ANSYS’ power integrity and reliability signoff technologies with Synopsys’ physical implementation solution for in-design usage.

While designers have been using ANSYS and Synopsys tools in combination for years, the integrated solution will enable mutual customers to apply power integrity and reliability signoff technologies earlier in the design flow … to deliver innovative, high-performance and reliable products faster, while reducing power, area and cost.

The integration of ANSYS’ platform for chip power and reliability signoff, ANSYS RedHawk, with Synopsys IC Compiler II, will provide users earlier signoff accuracy within the Synopsys design environment. This integration will enable rapid design exploration, design weakness detection, optimization and thermal-aware reliability through increased functionality within the place-and-route environment. The in-design power integrity and reliability signoff-driven flow will eliminate late design changes and ensure consistency with final chip-package-system signoff analyses with RedHawk.

John Lee, GM at ANSYS is quoted: “As the industry moves to more and more complex chips, signoff-driven rail analysis needs to be available sooner in the physical design flow just like timing and design rule checking. We believe partnering with Synopsys to bring our signoff technology into the Synopsys In-Design approach is the right way to accomplish this objective.”

Sassine Ghazi, SVP and co-GM of Design Group at Synopsys, is also quoted: “This partnership is a continued step in Synopsys’ strategy to bring more physical and signoff technologies earlier in the design flow within our Synopsys Digital Design Platform. Partnering with ANSYS enables Synopsys to quickly deliver a reliability and thermal-driven design flow that is critical for designing the next generation of semiconductors.”

Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, cheered the news: “TSMC collaborates with our EDA partners on silicon design solutions to enable our customers to achieve competitive performance, power and area for their next generation electronic products. This industry collaboration between Synopsys and ANSYS provides an opportunity for them to take the collaboration a step further by enabling reliability and thermal-driven physical design built on the industry’s popular physical implementation and signoff solutions.”

Hobson Bullman, VP and GM, TSG, ARM, also celebrated: “ARM has been a long-time user of both Synopsys and ANSYS technologies, which have helped in the development of some of the most sophisticated CPU cores available in the market. This announced partnership will enable our semiconductor partners to optimize our IP within their SoC designs earlier in the flow allowing more time to focus on reliable, robust and energy efficient designs.”

SA Hwang, GM of Design Technology, MediaTek, innovated: “Both Synopsys and ANSYS have been strong collaboration partners with MediaTek to manage increasing manufacturing complexity and to deliver designs on schedule while realizing aggressive performance, power and area goals. We believe this new partnership between Synopsys and ANSYS will enable MediaTek engineers to accelerate their pace of innovation while achieving further power, performance and area optimizations.”

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