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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Herb Reiter at EDPS: Multi-Die IC Design and Application

 
March 24th, 2016 by Peggy Aycinena


To speak with Herb Reiter about the rationale for multi-die packaging
is a chance to follow a logical and energetic continuum from first principles to a final conclusion. Namely, that as the era of the ASIC subsides, the era of the multi-die package will arrive full force.

Reiter, President of eda 2 asic, will be reiterating this line of thinking, in conjunction with a panel of like-minded experts, at the upcoming EDPS conference in Monterey on April 21st. In anticipation of that session – “Multi-Die IC Design and Application” – we spoke by phone this week. The conversation was compelling.

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WWJD – What process node are we at right now?

Herb Reiter – Ten days ago at the TSMC Symposium, [the company] was aggressively promoting their 10 nanometer and 7 nanometer nodes and showing all kinds of justifications: how much better, lower power dissipation, etc. They wanted to convey to the design community that continuing on Moore’s law is okay, but I am not convinced.

[Particularly because], Cliff Hou, VP of Design Enablement at TSMC, said the company now has 1000 people working in this area, engineers to manage the design flows, the libraries, and the infrastructure that’s needed for IC designers to design this next generation chip. And, of course, the [TSMC] team has to support a high-voltage version, a low-power version, versions for MEMS, for sensors, and everything needed for the right tools.

To put it simply, in my perspective, [this efforts proves] design is becoming more and more difficult, requires an enormous infrastructure, high education levels, and an increasingly long time to get to profits, and then only after incurring significant costs.

WWJD – It does all sound very dark.

Herb Reiter – The problem is, if you invest so much effort up front [in design] you need huge volumes to be cranked out. So far the smart phone has given us these huge volumes, but smart phone demand is leveling off.

What’s become important now is that your system be environmentally aware, and the best example of such a system is an automotive system. These systems have image sensors, all kinds of visualizations, all kinds of electronics – not to replace, but to augment the driver and help avoid accidents.

Decisions the human had previously made in a split second – Is this a critical situation? Am I going too fast? Do I need to initiate braking? – now need to be done by the on-board computer. The sensor sees an obstacle ahead and the computing device responds, but that computer needs to be [manufactured at] 10 or 7 nanometers to be fast enough, and consume low power.

WWJD – Why is low power so important in an automotive environment where you basically have an unlimited power source?

Herb Reiter – That is a good question. You have in the automotive environment, very high temperatures. These devices need to operate at up to 100 degrees centigrade.

But if you have a lot of power consumed in the chip at high temperatures, the failure rate will go through the roof. For systems in the automotive environment, however, reliability now as to be as good as perfect. Even better, in fact.

WWJD – We now need systems in automobiles that are as fail-safe as in aeronautics?

Herb Reiter – Yes, particularly if you look at autonomous cars, vehicles like Google and Ford are now building. For these [and other manufacturers], on-board intelligence is becoming the differentiator for new product lines.

[In fact], automotive systems can’t really go any faster or get any more comfortable, so they need to be differentiated with intelligence. Like smart phone where user friendliness and compute power have become the differentiators, cars must now be engineered with that same [end-point in mind].

WWJD – Certainly developing all of this offers job security to a lot of people.

Herb Reiter – Yes, there is big hope for the semiconductor industry here.

But consider, for smart phones we are speaking in the order of a billion units or more per year, where automobiles only sell fifty million to seventy million units per year worldwide. That’s a 20-to-1 comparison, smart phones to cars.

Yes, the car will contain much more electronics than a smart phone, but I don’t see a whole lot of standardization when there is no opportunity for high-volume design.

WWJD – And high-volume design is the only way to fund the huge numbers of requisite standards going forward?

Herb Reiter – If we don’t get de-facto standards lined up by one company, a government, or an industry association, we won’t be able to capitalize on economies of scale for developing automotive systems.

And look at the number of governments: effectively, there’s Europe, the U.S., Japan, and China – four major ‘powers’ from a nationality perspective, each having their own standards. Then take the 70 millions units and divide by these 3 or 4 governments, and you can see there’s less than 20 million units per player. It’s very difficult to establish standards with so few units in production.

WWJD – And this motivates the topic of your session at EDPS?

Herb Reiter – Yes, the conclusion is to put multiple die not on an IC, but in a package that offers modularity. You can plug in the die as needed, and help the automotive industry move forward.

And, this [strategy] has will help with IoT design, the other important application area where you need all kinds of sensors, wireless, and wired applications. Much more processing will be needed for these devices, and more memory, but none of these requirements can be addressed well with an SoC.

If you have multiple dies, however, you can put a particular sensor into the package, and add as much memory as you need. The processor can be faster or slower, and you can put different types of radios behind it. [The overall affect is] much more flexibility, with much more cost effectiveness and much quicker development.

WWJD – There’s more flexibility in the design when it’s built into a package, rather than an SoC?

Herb Reiter – Yes. Intel can put its processor into the package, complete [the design] with Micron or Hynix memory, a radio from Skyworks, and an ADC from Analog Devices or Maxim. You can build the entire system using die-level IP.

WWJD – So the IP block is now a system in its own right?

Herb Reiter – Yes, now it’s a bigger block. The user can combine these large building blocks and get to the final system much faster, and [achieve] better margins.

WWJD – Which was the argument in the first place for IP use and reuse.

Herb Reiter – Right. That was the argument made years ago when semiconductor IP first got started. But those building blocks today need to be manufactured at the latest technology nodes, and verified, and then the whole SoCs need to be verified. If you break it into multiples pieces, however, you have pre-approved building blocks.

I talked recently to a wireless designer for a smart phone. They have to qualify every radio that goes into a smart phone, which takes 6 months or more. If you have a radio die that’s pre-qualified, you will cut the verification from 6 months to 6 weeks. It’s becoming a major competitive advantage.

WWJD – Is it still an art, determining what is the optimum level to be working with IP blocks?

Herb Reiter – Remember that 20 years ago, the ITRS road map was focused on the component and transistor level. The concern, for instance, was the spacing between the wires.

But in the last go-around for the ITRS road map, they completely changed the approach. Previously, it was bottom up, but now it is top down. Now [the strategy] is to look at specific market segments: What do we need for automotive? For IoT applications? For other important markets?

The ITRS road map is going this way, with basically [all of these systems] derived from building blocks, which will enable the decision of how fine is the granularity needed for a particular set of IP blocks. The answer will come from knowing which market segment [you are addressing].

WWJD – It does seems a very elegant solution.

Herb Reiter – Yes, very elegant and very smart engineering.

You start by realizing the electronic system is getting more complex and more difficult to design, and therefore it is impossible for one engineer to understand every part of the system.

But if it is architected down to the [appropriate level], it does not matter if you re-design the tires, the seats, or the entire engine, you can much more quickly engineer the next generation of the design – and with fewer surprises – if you are only [working to reduce] the incompatibilities of the interfaces between the systems. It’s looking at the interface mechanism which becomes the focus of the design.

This is the strategy which we must go to for in automotive design, relying on building blocks and [standardized] interfaces. We need to get to building blocks that are pre-qualified and provide solutions that the market accepts. Otherwise, we will never catch up with the schedules, or control costs.

I’ve been chipping away at this [perspective] for over 8 years. At the start, my friends thought I was hallucinating. But now I am quite sure that just as ASIC technology took over the world, this multi-die technology will soon take over the world.

WWJD – Our discussion makes me think about Gary Smith’s long-time push to move the industry to system level design.

Herb Reiter – Yes, and it was Gary that brought me to EDPS. I really enjoy this conference because it is fairly small, but full of a lot of really smart people.

And I am very enthusiastic about my session this year, Multi-Die IC Design and Application. The bulk of the group is extremely package focused, because the creation of ICs is moving from silicon into packaging and then assembling the system.

Sophistication on the packaging side will require us to get much more mileage out of the capability that the silicon guys put into it.


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EDPS Session Panelists …

* Riko Radojcic, Multi-Die Solutions for Mobile Devices
* Dusan Petranovic [Mentor], Challenges in Modeling and Verification of 2.5D-3D and FOWLP
* Ivor Barber [Xilinx], Multi-Die Economics, Assembly & Test Challenges
* Asim Salim, Multi-Die ASIC SiP (system in package) Manufacturing
* Paul Silvestri [Amkor], Advanced Packaging: Architecture Paradigm Shift

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One Response to “Herb Reiter at EDPS: Multi-Die IC Design and Application”

  1. Bill Martin says:

    Peggy,

    Herb has been a constant force trying to move what many thought was an immovable rock. But Herb got some help with EUV and smaller node economics. :)

    I have heard the term ‘chiclets’ used for small IC IP blocks. An appropriate term.

    Chiclets offer many advantages:
    1. Already designed and working
    2. They prevent external ‘tweaking’ that often breaks something that might not be apparent immediately
    3. They can be packaged for higher level bread boarding or lab characterization (by end user if they have not used a specific ‘chiclet’ previously
    4. They can protect soft as well as hard IP since they are produced in silicon; rather than in netlist form
    5. They can be cheaper and immediately available: they do not need to be migrated to the latest technology node*.

    The lithography train has been a huge success for decades and we have all benefited from this. We need the next ‘train’ and it is denser packaging. Quickly looking at silicon and package costs over the years and you will see dramatic improvements in silicon (due to scaling, 300mm wafers, etc) based on 2D (X/Y area); but slower progress on package. Opening up to the third dimension (z) allows new thinking for 2.5/3D packaging options which have been long overdue since the 1970/80s MCM primarily used in military applications.

    Herb can take a victory lap!
    regards,
    Bill

    * I always thought this was inefficient: once a USB subsystem was working in 130nm (or 90nm), migration was a huge waste of resources just to get something working in a smaller node. Speed was not a driver since the specs already stated min/max for this IP to work in a system. The number of gates (controller) along with the AMS (PHY) was trivial and did not offer much in area or power savings….

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