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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Emulation: Mentor & Ansys change the game

July 16th, 2015 by Peggy Aycinena

On May 27th, Mentor released its Veloce Power Application software, which “replaces a file-based power analysis flow with a Dynamic Read Waveform API integration to power analysis tools. [The new] approach captures information from the power switching activity plot and transfers that data to power analysis tools, [enabling] accurate power calculation at the system level, better power exploration at RTL for power budgeting and trade-offs, and more accurate power analysis and sign-off at the gate level.

“The [previous] approach of running the emulator, creating the file, reading the file into the power analysis tool, and running the power analysis tool is now reduced to just the emulator and power analysis run times.”

Several weeks after this announcement, I had a chance at DAC to meet with Jean-Marie Brunet, head of marketing for Mentor’s Emulation Division, and his team. We had a very interesting chat about the company’s progress with the Veloce technology.

Brunet was emphatic: “Mentor graphics is currently the global leader in emulation, with all others trying to play catch up but not succeeding! Our May 27th Veloce Power Application [is a reflection of that leadership].

“The size of devices [being designed today] is growing quickly, with increasing amounts of software and complexity in that software. Today, emulation is the defacto standard for testing [devices] and doing early software verification, which is why what we announced on May 27th is pretty unique.

“Since the first of the year, some of our customers booting operating systems on [new] silicon are suddenly reporting 2-to-3x increases in power consumption, with some reporting increases up to orders of magnitude. At Mentor, we’ve looked at the situation along with a couple of our advanced customers and tried to understand why.

“What [we’re seeing] is that the methodology is broken. Most are using functional testbenches for power analysis, but there’s a problem – functional testbenches do not boot operating systems. Yet, it’s the dream of those advanced customers to load the entire chip at the RTL level [into the emulator], to boot the operating systems, run it at 300 million cycles or more, run the apps, and see how the device behaves.”

Brunet said the new Veloce Power Application offers help in two ways: “One is an activity plot, which is not just ‘rocket science’ from marketing. If you can run over 400 million cycles on an emulator, you can run full applications on the processor.

“[Today’s chips can have upwards of] 70 billions nets, and designers need to capture every net, every cycle, and every activity. Through [our activity plot], you can see the toggling rate. After Veloce is booted with the operating system, you’re looking live at the activity.”

“Not every emulator can do that.” Brunet noted. “Those [emulators on the market] using an FPGA approach are eliminated, so that means one [of our principle competitors] is out. The other [competitor’s] emulator can do it, but ours also has a second [feature] which they do not. We’re now computing activity from a dynamic standpoint, and then providing that data to the power tool.

“But we do not have a power analysis tool in-house, so we’re [partnering] with companies like ANSYS. We’ve launched an R&D collaboration with a companies that [can be seen as competitors] to create a Dynamic Read Waveform API.

“Now today, the two tools from the two companies – Mentor’s Veloce and ANSYS’ PowerArtist – talk through a binary tool integration. And now you can know the real power activity. You can boot your OS, first with switching activity, and then at the RTL level.”

I asked if customers already have access to the new technology.

Brunet said, “Yes. Some customers are deploying right now, with full production release scheduled for early Q4 of this year. These customers are seeing that they can run huge numbers of cycles on the emulator without having to go through [the time-consuming phase] of creating a file. They’re looking at power in booting the RTL, and can identify which modules are contributing to [power issues].”

“This is particularly important in the mobile market,” he added, “where the design challenges are tough. Where somebody is running software [on a new device], running new apps, but has no idea as to the amount of power that will be consumed in the process.”

Brunet ended with even more enthusiasm: “As recently as several years ago, the accuracy [needed for such things] was not there. But now the tools are much for accurate. Now you can see real switching at the RTL level in emulation.

“We believe our Veloce announcement and our partnering with ANSYS has become a real game changer in emulation!”


Additional voices …

EDA’s legendary Gary Smith is quoted in the May 27th Press Release: “The ITRS report, one of my many primary research projects, has emphasized the issues related to dynamic power for several years. A new approach to the transfer of power switching activity data captured during emulation is the right direction for the industry.”

Eric Selosse, VP/GM of Mentor’s Emulation Division, is also quoted: “Today we have redefined the power analysis flow. The Veloce Power Application is a proof point to show that a new methodology that captures real power consumption during emulation and effectively passes that information to power analysis tools is more efficient.”

Finally, Vic Kulkarni, an EDA legend in his own right and currently SVP/GM for the RTL Power Business Unit in the Apache Division of ANSYS, is quoted as well: “With our industry leading PowerArtist solution, we are delighted to be the premier partner in the Veloce Power Application ecosystem, and to work so closely with a technology leader in hardware emulation.”


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