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 What Would Joe Do?

Archive for June, 2014

DAC 2014: Advanced nodes and going back in time for a solution

Thursday, June 12th, 2014


In response to my blog this week about the June 5th panel at DAC, “Advanced Node Re-spins: Be Very afraid (maybe)“, Bill Martin, President/VP of Engineering at E-System Design, sent the following comments.


For 15 years, I was on the same process-node-jumping bandwagon. Always looking for that next node to help solve cost, performance, area and speed that might help with the overall schedule. Even in these older (larger) processes, each new process required 2x the resources (people, time, machines, etc.) to achieve tape out.

Fortunately, I was happily ‘stuck’ using VLSI Technology’s foundries, processing and wafers. Although we were not perfect, we did learn quickly to hone processes, models, design flows, etc., to minimize rework. But that world I knew was prior to the ASIC dis-aggregation that has taken place over the past 2 decades, and because there are pros and cons to that dis-aggregation, your summary of Thursday afternoon’s DAC panel brought back some pleasant memories, as well as nightmares. Clearly we need a new mindset!


Advanced node Re-spins: Be very afraid (maybe)

Tuesday, June 10th, 2014


UMass Amherst’s Sandip Kundu moderated a Thursday afternoon panel at DAC entitled, ‘Designing on Advanced Process Nodes: How many re-spins should you plan for?’

In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.

Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”

It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.

Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.


DAC 2014: Algorithms, Adjacencies, Animosities, World Peace

Thursday, June 5th, 2014


The June breezes were intense in San Francisco this week. The fog was swirling out at the Great Highway, and making itself known across town amidst the flags flying sharply over Moscone Center. The Electronic Design Automation and IP communities were out in force in and around South Hall, while thousands of edgy app developers were playing out their own dramas across the street and down the block in and around West Hall where Apple was holding court at the same time. Fourth and Howard was awash all week in hordes and gaggles of the people who are shaping the future of the world.

Algorithms – Perhaps as never before, algorithms were the number one topic at DAC this year, and in so many different shapes and sizes. Algorithms for high-level synthesis, algorithms for creating models, algorithms for translating physical data into guidelines for design, algorithms for translating assertions into verification metrics for more orderly validations, algorithms for encrypting and decoding, algorithms for compression and decompression, algorithms for converting approximate computational output into exactitude, algorithms for hearing, seeing, and even believing. In San Francisco this week at DAC, it was algorithms all the way down, everywhere you looked.

Adjacencies – The Design Automation Conference is all about ideas, and this year the principle idea was change. The Executive Committee re-shuffled the long-standing deck of cards that’s represented the most important topics at DAC over the last 50 years and came up instead with a whole new set of talking points.


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