Archive for April, 2014
Thursday, April 24th, 2014
Talking to ProPlus Design Solutions requires a long view of history over at least the last 20 years in EDA. In 1993, BTA, an EDA company focused on device model extraction and SPICE simulation, was founded with U.C. Berkeley’s Dr. Chenming Hu as Chairman of the Board. In 1999, BTA merged with Ultima, and became Celestry in 2001.
Finally, in 2003, the combined companies were acquired by Cadence Design Systems. Then in 2007, a new company called ProPlus was spun out of Cadence to support the original BSIMProPlus device modeling platform with roots going back to BTA/Celestry.
Current ProPlus CTO Bruce McGaughy earned his PhD at Cal with Chenming Hu as his advisor, served at both BTA and Celestry, and worked at Cadence, before joining ProPlus 6 years ago. I had a chance to talk with Dr. McGaughy in person last month in Silicon Valley. Our conversation covered a range of topics.
Monday, April 21st, 2014
In the moments prior to Cadence’s quarterly earnings call this afternoon, the company released news of the acquisition of Jasper Design Automation for $170 million, less $24 million in cash, and a small tremor rippled out across the EDA Nation.
Paraphrasing Cadence CEO Lip-Bu Tan in the early minutes of his 5pm ET earnings call: We are very pleased to announce a definitive agreement to acquire Jasper Design Automation. This will help us to further meet our customers’ needs for more advanced verification solutions, particularly today as verification now represents 70% of the cost of SoC development. Together, Cadence and Jasper can move forward, offering the strong formal verification solutions leading customers need. In addition, Cadence is also very pleased to be bringing on board the strong team at Jasper, a team with excellent real-world experience.
All good stuff, yes? So why any tremors in our beloved little EDA Nation?
Thursday, April 17th, 2014
Overlooking the inky calm of Monterey Bay, the lights of tethered boats in the marina reflecting in the shimmering waters below, Wally Rhines delivered a mesmerizing after-dinner keynote on Thursday night, a gift to an intimate group of EDPS attendees assembled in the low-slung Monterey Bay Yacht Club adjacent to the municipal pier.
It was textbook Rhines: a detailed re-telling of the last 50 years of the semiconductor industry with a log-log analysis of the validity of various versions of Moore’s Law, a dizzying display of data on shrinking feature sizes, and an adamant admonition that the law is, in fact, an economic learning curve with applicability that extends beyond the narrow confines of electronics.
From there, Rhines talked at length about what constitutes a process node, the gulf between Engineering’s obsession with gate length and Marketing’s obsession with world domination, and how reality got so out of whack with message that in recent years the ITRS had to step in and put an end to a war of claim versus counter-claim. Nonetheless, per Rhines, one company’s 16nm today is another company’s 14nm, as the murky physics behind the labels obfuscates to confuse the customer and confound the competition.
But the real core of Rhines’ talk was still to come: He addressed the issue of margins, head-on, across the entire spectrum of the semiconductor food chain, one micro-segment at a time. To do this to completion required many more charts, extensive additional analysis, and a lot more time. Yet, even as the hands of the clock over the bar inched well past 9 pm, no one in the room budged, yawned, or dozed – so complete was Rhines’ mastery of the material and command of the context. It was brilliant.
Thursday, April 10th, 2014
As a journalist, you often talk to product managers of EDA companies. Sometimes, you talk to VPs, SVPs, or even EVPs. On the rare occasion, you might event speak with a CEO. This last, being more likely if it’s the CEO of a small EDA company. Of course, these days small companies in the industry are harder and harder to come by, consolidation being the current national pastime across the width and breadth of the EDA Nation.
As a journalist, however, the kind of person you rarely talk to is someone in sales. And that’s not necessarily a bad thing.
On the rare occasion when a journalist talks to an EDA sales person, it’s usually at big vendor-sponsored dinners associated with large conferences, evening events set aside to entertain press, analysts, and customers where there’s some sort of company rep assigned to sit at each table. It’s on those rare occasions that a journalist might accidentally end up sitting next to, and talking to, someone from EDA Sales – all the way through the salad, the main course, the dessert, and even through the after-dinner entertainment.
And it’s during those rare encounters at big dinners that many journalists realize that the EDA industry they thought they knew, is a completely different kettle of fish, a completely different entity, from the one where EDA sales people live and work.
EDA Sales occupies a completely different EDA Nation from the one journalists hear about from EDA product managers, executives, or marcom specialists who busily spin narratives about the company specifically for the benefit of the press and the endearing little stories they write.
Thursday, April 3rd, 2014
There are lots of clever ways to tell you why it’s worth your while to attend EDPS in Monterey on April 17th and 18th. It’s less noisy than DAC, less vendor-specific than CDNLive, SNUG or U2U; less crowded than ISSCC; has fewer presentations than DVCon; and boasts no co-located events to confuse your schedule like at ISQED. But that doesn’t tell you why EDPS is worthwhile. It’s the list of speakers and the setting that should convince you to carve out some time on that Thursday and Friday to run down to Monterey – a scenic hour’s drive from Silicon Valley – to attend the 21st annual Electronic Design Process Symposium.
On Thursday, Wally Rhines is giving the keynote after dinner; during the day, Gary Smith’s moderating a session on design flow challenges that includes Frank Schirrmeister, John Swan, Gene Matter, Jim Kenney, and Naresh Sehgal; Sehgal’s leading a session on pre-silicon software development platforms that includes Camille Kokozaki, Shantanu Ganguly, Kumaraswamy Namburu, Schirrmeister, and Vicki Mitchell; Herb Reiter’s moderating a session on FinFETs, 3D-ICs, and FDSOI, that includes Jamil Kawa and Paul McLellan; and the kick-off keynote on Thursday morning will be given by Intel’s Chris Lawless talking about pre-silicon platforms for software development.
On Friday, Dan Nenni’s leading a whole day on IP that includes Martin Lund, Patrick Soheili, Warren Savage, Kurt Shuler, Lluis Paris, Carey Robertson, and Bernard Murphy. Finally, Aparna Dey is General Chair for EDPS. All together, that’s 24 people and a robust ecosystem of knowledge and experience comprising this year’s EDPS program.