Open side-bar Menu
 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Node2Node: Mentor’s Joe Sawicki

 
March 13th, 2014 by Peggy Aycinena

The following conversation with Joe Sawicki, VP/GM of Mentor Graphics’ Design-to-Silicon Division, looks at the complexities of deciding if and when a company should move down to the next process node. The interview was inspired by an upcoming panel at DAC, Designing on advanced process nodes: How many respins should you plan for?

Sawicki is an acknowledged expert in design and manufacturing, and “responsible for Mentor’s design-to-silicon products, including the Calibre physical verification and DFM platform, and the Tessent design-for-test product line.” I spoke to him by phone this week while he was traveling in Japan on business.


*****************

Moving down from node to node …


WWJD –
How does a company decide if the costs associated with porting their design efforts from one process node to the next are worth it?

Sawicki – Actually, up until the last few years, it was a trivial decision. When it was time to do the next chip, or you had a design that would enjoy having a cost reduction, virtually everyone marched down. Deciding whether you marched down on the first release of a node [from the foundry], or after the node had been established for a year and a half, fully depended on what market you were targeting.

WWJD – What were some of the metrics people looked at to make that decision?

Sawicki – Everything from lower power to lower cost. Depending on the application, for instance, power versus performance could be the starting point for looking at the trade-offs associated with the move.

It’s been about a decade, however, since this has been the case. Over the last couple of nodes – 20 and 16 nanometers, in particular – you’ve seen people debate for a long period of time before making the move, because it’s hard to know if the move will make things more costly per transistor or even a little less.

People are not getting the cost benefits out of 20 nanometers and 16, are not necessarily getting faster transistors because they can’t get the power off, and are left with integration problems. Still, people who really need more transistors and more functionality are moving to 20 – for instance, to support the whole 8-core processor [thing] needed in cell phones to drive all those apps.

And, those who need better integration or better power will find 16 attractive. They won’t get more transistors on the die – essentially at 16 nanometers it’s the same exact interconnect stack as at 20 – but they’ll get better power. By the way, the foundries are claiming a 10-percent integration improvement at 16, but that’s more about moving to finFETs than it is about better device [geometries].

WWJD – Will everybody eventually get to 20 and/or 16 nanometers?

Sawicki – I know whole design groups in large companies who won’t go below 28, while other companies are attempting to get better characteristics using FDSOI on 28 nanometers. It’s clear 28 will be a big node, but 16 will be a reasonable node. If I dug hard, I could name 20 to 30 companies who are going to 16 – or depending on the foundry, going to 14.

WWJD – A simple question, why is it so expensive to march down to the next node?

Sawicki – It’s almost entirely a lithography issue. To get the resolutions you need to get the pitch to get more transistors, we had to go to double patterning, which increased the amount of processing. And manufacturing finFETs have their own multiple patterning challenges, which will drive those costs up. What’s interesting now is what might come at 10 nanometers. That node might actually get us back to a cost-reduction node.

WWJD – You’re saying 20 and 16 nanometers are sufficiently problematic and costly that some companies are lingering at 28. Meanwhile, 10 nanometers may offer renewed economic benefits. So can a company that stopped at 28 nanometers jump straight to 10?

Sawicki – That’s really an interesting question. It can be done, but it’s hard and not for everyone.

There are some fairly big, popular companies whose strategy says they go with every other node. But the difference here, the challenge in jumping over two nodes from 28 to 10, is about building up adequate design experience around double patterning, and understanding how that impacts the process in terms of timing, resistivity, and capacitance.

WWJD – So there are advantages in progressing methodically from 28, to 20, to 16, and then to 10?

Sawicki – There are problems and processes associated with every move that have to be worked out between the EDA team, the design team, and the foundry. One thing that’s emphatically clear is that it’s easier to be a late comer to a node than to be an early adopter, because every move is a big leap.

WWJD – Is it good news for Mentor that 10 nanometers is on the horizon?

Sawicki – We’re doing a lot of work at 10 nanometers – not in the design space, but in the OPC space, where we’re having to come up to 4 or 5 different techniques. Whenever we move down a node, that’s a baseline for innovation. Fundamentally, when you’re innovating you’re able to capture value.

WWJD – Do you ever want to nudge your customers to move down a node?

Sawicki – Our customers couldn’t care less about our opinion in this area. What their EDA vendors tell them is an irrelevant calculation. If they can still monetize at 28 nanometers or 40, they will.

And because some nodes can have a history as long as 6 years, we continue to innovate on established nodes. That’s important because people can still get stuck, even at a big node like 28, having trouble with mixed-signal integration, or needing different strategies for lower power, or dealing with minor process variations.

WWJD – How exactly does a company know how much it’s going to cost to move to the next node?

Sawicki – It’s a mix of things. First you get your basic wafer pricing. Then, given that price, how big is the die going to be? Then you take into consideration the characteristics of the standard cell and the interconnect stack, make estimates of the design at this size and how many per wafer, and look at the costs. Then you look at the Spice deck, and timing considerations, and ask: Does it or doesn’t it make sense to make the move?

The decision requires mixing a lot of equations with a basic foundation of understanding and experience. And it’s quite precise, because you can’t afford to muck around in making this decision.

WWJD – Do people ever get it wrong?

Sawicki – It’s not so much that they’re wrong in their calculations. What they get wrong is, if they go early into a node and there is a problem with yield. Back in the 130-nanometer days, there were some major problems with yield. This is actually an area where we can give people the tools, so they can figure it out quickly.

WWJD – Why not be a “mid-stream” adopter, rather than an early or late?

Sawicki – It all depends on your market, and on what makes sense. Most microcontrollers in automobiles, for instance, are at 65 nanometers, because that’s a market that doesn’t want technology risk.

But if you look at cell phones, at what you might do if you actually came out with a cell phone process that allows 2 days rather than 1 day of battery life, the answer’s pretty obvious – that’s something that would drive great profitability, so go to the lower node. As long as you understand your market well, the decision [should be clear].

There can be problems, of course – certainly 130 nanometers was an epic example of what can go wrong – but in semiconductors, if you’re the first into a market window that moves as quickly as consumer products, as an early adopter you’ll capture 110 percent of the profitability.

*****************

Related posts:

Tags: , ,

Leave a Reply

Your email address will not be published. Required fields are marked *


*

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy