Archive for 2013
Thursday, February 28th, 2013
I don’t know about you, but I thought DVCon 2013 in San Jose this week was super. There was a lot of energy, I never heard anybody say the tools are broken (something industry pundits have been droning on about for years), attendance at the conference set a new record, both verification and design guys seemed to indicate that verification is still important enough to remain discrete from design, and SystemVerilog is fulfilling its promise.
The following list of 15 sound bites is not a complete representation of all that was said or debated at DVCon. Nonetheless, it’s an interesting list and reflects some of the information and opinions showcased during the week.
Thursday, February 28th, 2013
Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of “Best Practices in Verification Planning.”
Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous. The Cadence-sponsored lunch and panel discussion, moderated by Cadence’s John Brennan, included Verilab’s Jason Sprott, Cadence’s Mike Stellfox, ParadigmWorks’ Ambar Sarkar, Maxim’s Neyaz Khan, Oski Technology’s Vigyan Singhal, and Xilinx’ Meirav Nitzan. The panelists began with an overview of their experiences.
Thursday, February 21st, 2013
If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.
“Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”
I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”
Thursday, February 21st, 2013
You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.
If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.
Thursday, February 14th, 2013
These several months are a great time to learn how the innovations of Lynn Conway and Carver Mead influenced the arc of history of the microelectronics industry.
The entire fall issue of IEEE’s Solid State Circuits Magazine is dedicated to Lynn Conway’s contributions to VLSI design and manufacturing. Monday morning, February 18th, Carver Mead will be keynoting at the opening plenary session of ISSCC in San Francisco. And next month at DATE 2013 in Grenoble, a panel entitled “The Heritage of Mead & Conway” will take place in Tuesday, March 19th.
The DATE panel will be moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, and will include IMEC’s Hugo de Man, Synopsys’ Antun Domic, U.C. Berkeley’s Jan Rabaey, CMP’s Bernard Courtois, and Columbia’s Luca Carloni. Per the conference program, the panel will discuss “what has remained the same [since the Mead-Conway VLSI Revolution], what was missed, what has changed, and what lies ahead.”
Thursday, February 14th, 2013
In case you didn’t know, U.C. Berkeley is the center of the world. That’s why several hundred people attend the Berkeley EECS Annual Research Symposium each February, and this year is no exception. If you were here on campus with me this morning, you would be hearing – yet again – that there’s no better School of Engineering than Berkeley’s, no better EECS alumni than Berkeley’s, no better weather in the world than on this campus overlooking the glorious San Francisco Bay, and no more hip-or-hipster place to be. Anywhere.
BEARS 2013 started off today with Prof. David Culler acknowledging this year’s distinguished EECS Alumni Awards. Recipients include SanDisk Co-founder, President & CEO Sanjay Mehrotra; the co-inventor of a type of binary search tree, championship aerobatic pilot, and University of Washington professor Cecilia Aragon; and Sendmail developer Eric Allman, who mentioned from the podium that he may have helped create email but he’s not to blame for spam. Allman also noted that everybody who comes to Cal as a student is more lucky than smart to be here.
Yeah, right. How can that be the case if U.C. Berkeley continues to describe itself as the center of the technology universe, where swarms, networks, tablets, and big data, among a host of other innovations, were all developed and refined?
Having said these things, let me reminisce about my father, who by cosmic coincidence would turn 90 this week if he were still alive. Back in September 1940, when he was a desperately poor, 17-year-old fatherless child of the Depression, he showed up in this town to pursue a degree in biology and hopefully become a doctor. His widowed mother had lost the family’s 10 acres of orange trees, their only source of income, to the foreclosure agents of the Bank of Italy back in 1935, and my father brought that humiliation to Berkeley with him, along with 2 pencils, a pen, and one shabby change of clothing.
Wednesday, February 6th, 2013
Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it’s about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It’s also the amount of time Stan’s been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.
When I spoke with Stan by phone earlier this week, I asked if he’s been to every single conference since then. He laughed and said, “Absolutely! Looking back to 1988 – despite all of the mergers, and the coming together of various conferences, and the end of the HDL wars – I’ve been to every one of them!”
There’s nobody else who’s been to them all? Stan laughed again, “I don’t think so. They’ve either retired, or left the industry. Although I do think Dennis Brophy has been coming for a long time, but probably not all the way back to the beginning.”
Where was the first conference held in 1988? Stan said, “It was in Newport Beach. Why? Who knows. Back in the day, a number of meetings were held in Newport Beach. Maybe it was a destination, or maybe it was because there were a lot of defense contractors in the area. Remember that VHDL-87 had just come out and the language had a connection to the Department of Defense.”
Monday, February 4th, 2013
Breker Verification Systems VP Tom Anderson presented a concise tutorial on low-power SOC verification at DesignCon on January 30th. He began by laying out the challenges of low-power design, with an eye to the verification problems associated with various strategies:
Low-power SOC verification …
The need for low-power design is ubiquitous, with today’s plethora of consumer devices being battery-powered. ‘Big iron’ machines in modern data centers are also driving the need for low-power chips. As well, governments worldwide – especially in Europe – are passing ‘green’ laws; if you’re building a ‘big iron’ class of machine, you may be required by law to meet specified power limits.
There are various techniques emerging to meet these needs. Circuit-level design strategies include special transistor and cell design for non-critical paths. Different voltage thresholds are also an option, yielding a variety of performance levels and power consumption at different points on-chip; designers can make a one-time trade-off between performance level and path options on-chip. These techniques have little or no impact on functional verification. Other strategies, however, do.
Thursday, January 31st, 2013
Just past 8:00 am in the Santa Clara Convention Center on Wednesday, January 30th, I had the good luck to run into IEC’s Dr. Barry Sullivan, long-time leader at DesignCon. Conversation’s always relaxed in that hour at any conference, and so it was with Barry. I asked him how things go with DesignCon, now that it’s owned and operated by UBM.
[Barry’s tenure with the conference predates the 2010 purchase of the conference by UBM, discussed here in a blog posted at the time by former EE Times Editor Nic Mokhoff.]
Barry said that UBM’s skill set is exactly aligned with the needs of DesignCon, and that’s a good thing. He said having a media company like UBM in charge is excellent for the conference. In the years prior to the acquisition, Barry said, the conference would sometimes have to “beg” the press to cover the event. With UBM at the helm, however, he said press coverage has been stupendous. I asked Barry if he thought DesignCon was out to replace DAC.
Wednesday, January 23rd, 2013
Each time around, it’s an interesting exercise to see what conferences are being co-located with DAC, and this year is no different. From May 31st to June 2nd in Austin, the 2013 Electronic System Level Synthesis Conference [ESLsyn] will be co-located with the 50th Design Automation Conference. That’s a particularly interesting choice, because after so many years of ESL enthusiasts positioning system-level design at the center of all things EDA, why does it still need its own conference?
Well, let’s look at the organizers’ description of the meeting: “ESLsyn focuses on automated system design methods that enable efficient modeling, synthesis, exploration and verification of systems from high-level specifications down to lower level implementations.”
Okay. That’s sounds good. But, again, isn’t that stuff covered in a host of different sessions at DAC itself, in particular in Tracks EDA1 and EDA2?