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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Hybrid ATPG/LBIST: Mentor says 1 + 1 = 1.3

November 21st, 2013 by Peggy Aycinena

Mentor Graphics has just posted a very interesting white paper on their website that discusses the advantages of combining ATPG and logic BIST to produce improved test coverage: Improve Logic Test with a Hybrid ATPG/BIST Solution, by Ron Press and Vidya Neerkundar.

The paper’s a good read for several reasons. There’s a brief, but accessible explanation of both ATPG and logic BIST, and then an equally accessible explanation of the benefits of combining the two to create a hybrid test approach.

This week, I spoke with Mentor’s Steve Pateras and Gene Forte about the paper and asked why, at this late date in the development of ATPG [automatic test pattern generation] and BIST [built-in self test], the paper starts with basic explanations of these two seemingly well-established test strategies.

Pateras said, “It’s true, a large number of designers do understand ATPG, but that is less so with BIST, which has been more of a niche usage. Today, most designers understand the need for mainstream DFT [design for test], but it is ATPG that has driven the adoption of DFT, not BIST.

“It’s not that designers disapprove of BIST, it’s just less well-known from a detailed implementation point of view, particularly from an IP block perspective. For that, we still see ourselves in a missionary mode and the authors of the paper wanted to be thorough, because designers need to understand both [to better use our hybrid approach]. ”

To clarify, Pateras acknowledged that memory BIST is now “ubiquitous” and has helped reduce ATE testing requirements, but logic BIST is not yet widely used. Things are changing here, however.

“The explosive growth in mission-critical automotive applications, things like steering, air bags, and braking,” he said, “along with the need for system-test requirements, has meant there’s far more motivation for logic BIST.”

“Despite vast improvements in data compression for ATPG,” I asked.

Pateras said, “Yes, over recent years it’s gone from a compression of 5x to a compression of 5000x, and that’s been important because the chips have grown so large.”

With that growth, he noted, the need for built-in self test has also increased but the reluctance still lingers. Per Pateras, “With this white paper, we want to demystify and debunk the impression that logic BIST is slow. Because one of the original flows from LogicVision was complex, and came with a large learning curve, initial adoption was stalled.

“Today, however, we are saying that our hybrid solution that combines ATPG and logic BIST is almost as easy as [stand-alone] ATPG. If you’re using our TestKompress flow for ATPG, adding logic BIST to that flow is incremental. It uses the same scan chains, clocking, and simulation engine, and they’re both hierarchical.

“That is why Mentor Graphics is moving forward in many different areas of test, combining our IP for compression and logic BIST to reduce area and increase efficiency. We just released this hybrid capability 6 months ago, although the approach has been in beta for a year or more, so we want to spread the word.”

“Are there any downsides to the hybrid approach,” I asked.

Pateras said, “No. Once you have built both into the system, you can choose the one that’s appropriate, which is the beauty of this approach. Still there is some push back. Designers may just want to put logic BIST into certain cores, removing any unknown states, which gives better ATPG results. Using logic BIST in particular cores allows you to divide and conquer the problem.”

“So a good designer enhances the design for both techniques,” I asked.

Steve said, “Actually, when you make a clean DFT design for logic BIST, it’s good all over.”

“And the cost in real estate to implement logic BIST,” I asked.

Gene Forte responded: “If the overhead you require for compression is 1, and the overhead you require for BIST is 1, the sum of the two is far less than 2.

“With our hybrid approach, it’s more like 1 plus 1 equals 1.3.”


White Paper Conclusion …

“Using a combination of embedded compression ATPG and logic BIST, you can test/retest chips during burn-in and in-system, you get very low DPM, and can check for small delay, timing-aware, cell-aware, and path delay defects. The designs that require both ATPG compression and LBIST can use combined hardware to achieve the test goals by sharing the PRPG and compactor, which provides an additional reduction in hardware cost.

“Because more designs are using this hybrid ATPG/LBIST approach, EDA vendors like Mentor Graphics now provide tools to reuse logic between embedded compression ATPG and LBIST. A number of automotive and medical designs are being tested with a combination of deterministic ATPG and pseudo-random LBIST patterns. Results showed the same high coverage as ATPG independently running, but with a shorter test time than when ATPG was run alone.

“In addition, the LBIST infrastructure makes ATPG and compression more efficient. The hybrid methodology may require more development time and more chip area to support LBIST, and test time reduction might vary from one block to another. The tradeoff is that adopting a hybrid methodology provides a higher quality test with a high level of flexibility.”


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