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Archive for September 5th, 2013

Fall Calendar Update: The pace quickens

Thursday, September 5th, 2013

 

Okay, summer’s over, September has arrived, and it’s time to figure out where you’re going to go over the next few months, conference wise. Some events are imminent, but others are a ways out, giving you time to think about registering and attending. Some events are vendor neutral, while others are vendor specific, which doesn’t preclude a chance to learn stuff. Although this list is lengthy, it isn’t comprehensive.

* ITC 2013
International Test Conference
Anaheim – September 8-12

* IDF 2013
Intel Developers Forum
San Francisco – September 10-12

* SNUG Taiwan
Hsinchu – September 10-11

* CDNLive China 2013
Beijing – September 10

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Herb Reiter: The three-legged stool of Technology Choices

Thursday, September 5th, 2013

 

Herb Reiter, founder and president of eda2asic, has been in the semiconductor and EDA industry for 30+ years, including stints at Barcelona Design, Viewlogic, Synopsys, VLSI Technology, and National Semiconductor. In the last few years, Reiter’s work has focused on SOI, 2.5/3D ICs, and FinFET topics in semiconductor design and manufacturing. Straightforward enough, until you realize that these are significantly different ‘3D’ technologies, where ‘3D’ means different things to different people.

In a recent phone call, I asked Reiter to distinguish between what he calls the “three legs” of technology choices and to weigh in on which “leg” is most likely to succeed.

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Fully-depleted SOI …

Per Reiter, “The original technology was partially-depleted SOI, a fairly thin film of silicon on top of a thin insulating layer. IBM came up with the idea, because substrate capacitance was slowing their chips down. They realized if they put in the insulating layer, they wouldn’t have to worry about substrate capacitance, because the oxide layer would insulate things.

“The planar transistor gate cannot reach all of the electrons in an 80-nanometer channel, cannot fully control the flow, and causes what we called ‘body-effect’ and ‘kink-effect’ design challenges. That’s why partially-depleted SOI was not widely used. So fully-depleted silicon on insulator, FDSOI, was introduced. It only has about a 20-nanometer active film on top of the oxide layer. The gate is sitting on top of the active film and can control all of the electrons passing through the source/drain channel, which is why it’s called fully-depleted SOI.

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