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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Cliff Cummings: His teaching is gift to the industry

 
August 28th, 2013 by Peggy Aycinena

Perfectly suited by nature to teaching, when affable Cliff Cummings steps up to conduct his Verilog course, the class is in for a treat. From the get-go, Cliff establishes a tone of respect, humor, and openness to questions of any kind. He encourages students to interrupt when they don’t understand, to stand up, sit down, resort to coffee and/or carbs, and in all ways to relax and enjoy the learning experience.

There’s something additional, however, that Cliff brings to his inspired task of teaching and that’s his decades of involvement with the Verilog language, its evolution, standards, and implementation. What Cliff Cummings doesn’t know about Verilog and SystemVerilog, isn’t worth knowing. Period.

This week, Cliff is teaching Verilog-2001 Design & Best Coding Practices in Silicon Valley – specifically, in the offices of EDA Direct – and I’ve been lucky enough to attend. Not being a Verilog expert, I approached the class with some trepidation, but found to my delight that I was not the only one among the 8 engineers in the room “new” to the language. We’re all engineers, but we’re not all Verilog designers and hence it’s a class perfectly suited to our skills, interests, and goals.

The particular class I’m attending is 3 days long, runs 9 to 5, and includes many hours of lecture (with plenty of breaks), as well as a heavy dose of lab work. Students are given a ponderously sized binder with a copy of each and every one of the slides, a comprehensive lab workbook authored by Cummings, and a quick reference guide to the Verilog Language authored by Stuart Sutherland.

In addition, each student is provided with a laptop loaded with Mentor Graphic’s Questa, although the class is agnostic with respect to the simulators. Cliff’s teaching materials and lecture address Questa, Synopsys’ VCS and Cadence’s Incisive. If a student’s employer uses either Synopsys or Cadence, and permissions have been arranged prior to the class, the student can log into their company’s server and run the labs that way.

In the class I’m attending, everybody attacked their labs with enthusiasm (well, most) and that’s totally because of the no-fear atmosphere that Cliff established from the opening bell. He’s clearly a master at making people feel comfortable with learning, which is not surprising given that he’s been teaching these kinds of classes since 1992. He told me he got into the work by taking the first-ever Verilog training course at Tektronix in Beaverton, Oregon, where he worked. Verilog was new and the company had just switched tools.

“They told me,” Cliff recalled, “to pay close attention in the class because I’d be teaching the material next. I was a designer in their ASIC consulting group and was already using the company’s internal languages. But the group was small and there were few other candidates for the job, so they decided I was going to be the one. After mastering the language, I started teaching Verilog internally.”

Cliff laughed and added, “I would not have wanted to be in one of my own early classes. It was not at all pretty, because I’d only taken the training once and was not an expert. However, they needed help and I filled the gap, including [providing] Verilog support across the company.”

Cummings acknowledged he’s living proof that the best way to learn a body of material is to teach it. And teach he did, from 1992 to 1994 at Tektronix, in and around his design work, and from 1994 to 1996 at Qualis, a 2-man VHDL contracting team before Cliff joined.

“I had already given papers at the Verilog conference that later morphed into HDLCon and then DVCon,” Cliff said, “so I was able to bring the Verilog credibility to Qualis that they needed.”

By 1996, however, Cliff felt he was ready to go out on his own as a contract designer and founded Sunburst Design. Straightaway an early client, inFocus, talked him into doing a VHDL design: “I resisted the job because I did not know VHDL, but they said I understood design well enough do it and that’s how I learned VHDL. Meanwhile, I continued to teach Verilog classes, because I wanted the focus at Sunburst to be teaching as well as design.”

Cliff laughed again when I asked how he came up with the name: “I lived in Beaverton which sits on the ‘Sunset Corridor’ that runs from Portland to the Pacific coast, so I was going to call the company Sunset Design. But after a name search, I discovered it was available in every county but mine, so I went with Sunburst Design. The name turned out to be a fortuitous choice. Sunset is about slowing down, but Sunburst is about big outputs of energy and I liked that.”

Now almost 2 decades later, Sunburst Design continues to thrive. Cummings is in demand everywhere, teaching both Verilog and SystemVerilog multi-day courses (usually simulator agnostic) and half-day seminars (usually simulator specific) around the world – in multiple cities in the U.S., Canada, Costa Rica, and throughout Europe, as well as an astonishing number of cities in Israel, India, Southeast Asia, China, and Japan.

In fact, after this week’s Verilog course here in Silicon Valley, Cummings is heading across the International Dateline to teach a course next week in Penang, Malaysia. From there, he’ll return to Silicon Valley to teach yet another course before finally returning home to Provo, Utah. (Cliff relocated Sunburst Design from Oregon to Utah in 2011 to be closer to family.)

I asked Cliff if he’s got a lot of frequent flier miles and he laughed: “I used to rack up a lot of miles on Alaska Airlines when we lived in Oregon, but now it’s all going to Delta. There’s no doubt, however, if my miles were all on one airline, I would be well into the Million Mile Club.”

As most of Cliff’s time is taken up these days with teaching (and racking up frequent flier miles), I asked him how he keeps up with developments in the industry. He said there are several important conferences that provide critical learning, SNUG and DVCon, but DAC not so much.

“Most papers are presented at DAC by guys with emails that end with dot-edu,” Cliff said, “and they are usually petri-net ideas that are more theoretical than practical. DVCon and SNUG are the places where practical ideas are discussed. Of course, I learn the most from my students. Every single time I teach a course, questions from students who are working in the field end up teaching me something new.”

One of the principle reasons Cliff Cummings is so much in demand is because of his long-time involvement with the IEEE Verilog standard 1364 committee, going all the way back to 1994. Throughout the evolution of the language, and the emergence of SystemVerilog and the associated UVM, Cliff has been a leading voice among many distinguished voices working for improvement and usability of the language including Phil Moorby (designer of Verilog),  Mike MacNamera, Maq Mannan, John Williams, Yatin TrivediGabe Moretti, Stu Sutherland, John Sanguinetti, Peter Eichenberger, Don Mills, Heath ChambersStefen Boyd, and Dennis Brophy.

I asked Cliff if he ever grows frustrated with the legendary pace (read, “snail’s pace”) associated with evolving IEEE standards. He said the pace may be slow, but “people wouldn’t have given Verilog the time of day if it hadn’t been an IEEE standard. It’s that simple.”

Meanwhile, Cummings is the rare designer who can compare and contrast VHDL and Verilog. As the IEEE Verilog standard 1364 was refined and improved, he worked to add the best aspects of VHDL into Verilog and to keep the worst aspects out. He told me that back when he was working in VHDL, he kept a file of the positive aspects of the language and a second file called VHDLyuck.

When asked if I could put that particular factoid into print, he laughed and said, “Of course. Everybody knows I hate VHDL!”

Nonetheless, Cliff Cummings is not afraid to critique Verilog, its poor handling of signed types and a certain “looseness” that can contribute to coding errors.  “VHDL is so structured,” he said, “it’s hard to even begin to play, but Verilog actually lets you play a little too loosely. There’s a lot of room for error in Verilog.

“Nonetheless, Verilog is better for innovators and innovative design,” he said, adding an emphatic caveat, “If you know what you’re doing!”

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To learn more …

* Register for upcoming Verilog-2001, SystemVerilog, or SystemVerilog OVM/UMV classes here on the Sunburst Design website.

* Read “The IEEE Verilog 1364-2001 Standard – What’s New, and Why You Need It” here on Stuart Sutherland’s website.


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