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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

FinFETs: Steptoe says bring ‘em on

August 15th, 2013 by Peggy Aycinena

Kevin Steptoe is VP of Engineering at Sondrel, a global chip-design consultancy based in Reading, U.K. We spoke this morning by phone about the future of FinFETs, in particular Steptoe’s reaction to my blog posted earlier this month, FinFETs: Yes, No, Maybe.

Steptoe said there’s nothing maybe about FinFETs. They are most definitely “an absolute yes” – revolutionary and disruptive as they may be – and offer great promise for the future of chip design, manufacturing, and deployment. And he said, his enthusiasm for the technology is not just from Sondrel’s point of view, but from his own personal involvement in the industry that extends back several decades.

Per Steptoe: “As the world’s increasingly insatiable demand for mobile, tablet-based, higher frequency devices ramps up, the predominant challenges for engineers and designers translate into fears of leakage power and performance. The FinFET, in its construction, addresses these challenges and makes mobile devices dramatically more possible.

“[In fact], the control of the short-channel affect and suppression of leakage actually simplifies things, so engineers will have the opportunity to achieve much higher [transistor] density, much lower power, and similar-or-increased performance levels. We see FinFETs as a win all the way around, a no-brainer that will fully live up to what it says on the tin: With FinFETS you will design ever larger devices with an ever higher power profile.”

All that optimism aside, I asked if manufacturing challenges are a concern.

Steptoe said, “There have been test devices made [and analyzed] and the question marks over the manufacturing process are no longer there. Yes, the costs of manufacturing will increase, but by no more than 3-to-5 percent. So the promise is great, particularly at 14 nanometers. I’m even hearing anecdotally that FinFETs are being demonstrated at nodes as low as 3 nanometer.

“Most importantly, I’m really encouraged that both the IP providers and the tool providers have seen these things coming for a while, and have been doing a lot of work to ensure that the tool flows will be there, even taking into account the serious side effects of mechanical stress and so one in the abstraction models. That modest cost increase of 3-to-5 percent is going to give us 37% faster devices with a complete zeroing out of leakage.

“You will also have the opportunity to use fewer processors. The huge designs being built today for signal processing in specialized areas such as broadcasting and satellite transmission really consumer a lot of power. They’re massive in terms of their design complexity, with many hundreds of them on a board, on a rack, in a room. When you realize the problems here, you see what FinFETs clearly offer, we won’t have to worry about the power/performance points that have been so challenging at the smaller nodes. Engineers will now have the opportunity to use fewer processors in their designs at higher voltages, instead of using many multiprocessors on a chip at lower voltages.”

With the admiration normally thrown at multicore devices, I asked why engineers would want to go with fewer processors.

Steptoe said, “Because you can run things faster with more instructions per second, and you can have much higher frequencies of signal processing and thereby achieve area savings. FinFETs won’t drive multiprocessor chips away, but they will allow exploration of a space where processor frequency [does not limit] performance. It’s the most radical shift in semiconductor technology since the start of the industry.”

Given such a radical shift, will retooling for FinFETs be prohibitively expensive and how great are the challenges, rated on a scale from 1 to 10?

Steptoe said the answers differ depending on which part of the design process you look at: “In terms of tooling, we need to improve the abstractions, with a difficulty level of 4 or 5. We wouldn’t dream these days of doing a SPICE simulation of a modern, complex digital chip so we abstract the model to a higher level and use static timing analysis. In making that abstraction, we’ve simplified and can perform much faster analysis more suitable to the size of the design.”

Steptoe added, “I’m pleased to see that all of the EDA providers have been working on this topic for a long time, so by the time the consumer of EDA tools is ready – whether you’re thinking in terms of the fabless design houses or the network processing design houses – by the time we are ready to use the tools, the abstractions will be so complete,  the design flow will appear to be the same.”

He offered an analogy: “In the old days, taking photographs required you to buy a roll of film, put it into the camera, and when you had taken all of your pictures, to send the roll away from processing. The film manufacturers worried about how the imaging chemical worked, you didn’t have to.

“For the consumers of EDA tools in the FinFET era, it will be the same. I will still need to know how to synthesize and partition the design, how to run the place-and-route tools, how to use a clock re-synthesis tool, how to budget in timing, how to get the parasitics out, and how to close the design. But the flow will not have changed from the point of view of the users.

“Inside the tools, your Mentors, your Synopsyses, your Cadences certainly will have been working in their labs to make sure the tools work. The consumer won’t actually see any difference in designing to a 28-nanometer CMOS process versus a 14-nanometer FinFET.”

“However,” Steptoe warned, “in terms of IP the actual design and creation will be hard, more like a 9 in difficulty, on a scale from 1 to 10. The key will be in how the IP vendors provide the physical and timing models of FinFET-based devices to the design community – the SPICE models, the TCAD models, and the modeling of the devices in the physical mask construction.

“This is going to be the tough bit, the [burden] on the IP providers. But again, referring to my camera film analogy, from the consumer’s point of view, no one need worry about it. They will get it done, and they’ll get it done quickly.

“You will see the transition to FinFETs take place at such a breathtaking speed, they will be fully implemented in just the next year or two. And even then, the fabs, IP providers, and EDA suppliers will attempt to introduce all of this change with the least disruption for the consumers, the maximum benefit with the minimum impact.”

Asked if Sondrel is worried about all of this disruptive change, Steptoe was adamant in his response: “We are delighted. When it comes to FinFETs, we say bring ’em on!”


Bio …

Kevin Steptoe has been instrumental in the start and success of some of the most prominent names in EDA in Europe: Cadence Design Systems, Chronologic Simulation, Avanti, and Magma Design Automation. He has held a variety of general management and executive roles in these organizations including sales, marketing, product development, and application engineering management. He also has considerable international experience in managing large sales support teams across geographies including Japan, Asia, China, India, and the U.S. In addition, Steptoe is a visiting professor at Queen Mary College University London.


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