FinFETs: Yes, No, Maybe
July 25th, 2013 by Peggy Aycinena
Ed Sperling, Editorial Director for Semiconductor Manufacturing and Design Community, moderated a breakfast panel on Tuesday morning, June 4th, at DAC. Having missed the bulk of the event, I was fortunate to have a chance later to review the slides of the five speakers: Cavium Networks VP Anil Jain, GlobalFoundries VP Subramani Kengeri and Director Kelvin Low, and Synopsys VP Raymond Leung and Senior Director Bari Biswas.
Having now gone through the slide deck twice, I’ve come away with a set of conflicting messages. On the one hand, the challenges of FinFET implementation are so great there is still much to be done, and the promise of the technology is yet to be fully proven. On the other hand, the synergy between GlobalFoundries and Synopsys is so excellent the challenges associated with FinFET implementation are definitely being met. So which is the more accurate message?
According to Cavium’s Anil Jain, perhaps the first message, although he clearly acknowledged the need: “Planar technologies are running out of steam because a) there’s not enough transistor performance increase from generation to generation of process nodes, b) there’s not enough voltage and power scaling, c) sub-threshold leakage current density is increasing substantially from node to node, and d) across-the-wafer and on-chip variation increases are affecting design closure and parametric product yield.”
Jain also acknowledged that with FinFETs, “a) ION increases substantially on a per unit basis because the channel surface extends into a 3rd dimension offering potential performance benefits, b) there are substantial sub-threshold leakage advantages and reduced short-channel effects, and therefore less leaky digital circuits can be designed, c) you get steep sub-threshold slopes that enable lower VTs with the same, or less, leakage and therefore potential for voltage scaling, and d) reduced variations results in better yields.”
Unfortunately, also according to Jain, “FinFETs are not a slam-dunk. Good performance is [achieved] at the expense of dynamic power. There are big improvements in leakage power, but electro-migration is still a big challenge. [It’s not clear] how we can control dynamic power and EM. And FinFETs are showing increased overlap parasitics, which is not a good trend.”
Hence what Anil Jain had to offer on Ed Sperling’s panel was not all goodness and light: FinFETs still need a lot of work. Period.
The next 4 speakers, however, from GlobalFoundries and Synopsys were far more definitive in their messaging: FinFETs are coming online not just because they’re needed, but because they’re distinctly possible. Some sound bites from their slides:
“GlobalFoundries’ FinFET Technology Architecture is optimized to solve power density, cost and reliability issues in FinFETS.”
“Synopsys is actively developing FinFET IP, standard cells and SRAMs. Synopsys is working closely with GlobalFoundries to enable the 14XM process with a complete IP portfolio.”
“Compared to planar, Synopsys’ FinFET test chips are showing better drive, lower voltage operation, and lower power consumption. Early silicon characterization results validate the benefits of FinFET technology relative to planar.”
“Synopsys’ FinFET Collaboration Model – StarRC, HSPICE and TCAD collaboration with foundries – is making adoption of FinFET transparent to design teams.”
“GlobalFoundries and Synopsys [offer] a comprehensive FinFET Solution: Tools, Flows and IP, collaborating with every early adopter with FinFET-aware tools, process technology development with TCAD, design tools with the Galaxy Implementation platform, and FinFET-ready IP.”
Do you see my point? This is confusing.
Cavium says there’s lots to be done, and motivation to do it, but they’re also saying it’s not clear that FinFETs are the answer. The jury’s still out and the answer on FinFETs might end up being No.
GlobalFoundries and Synopsys, on the other hand, are saying lots has already been done, lots is being done right now, and although there is more work ahead, FinFETs can and will get it done, and soon. The jury’s decided and the answer on FinFETs is Yes.
So yeah, confusing, and it matters not about a set of slides. What matters is where do you go from here, on what technology do you bet your design, and how do you convince your design team to ramp up for a possibly risky new paradigm?
Either you’re going to need a really good jury to sort it all out, or some really good luck, or both.
Tags: Anil Jain, Bari Biswas, finFET, GlobalFoundries, Kelvin Low, Raymond Leung, Subramani Kengeri, Synopsys