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Archive for May 30th, 2013

DAC 2013: EDA news in anticipation of Austin

Thursday, May 30th, 2013


** Aldec announced the launch of Spec-TRACER, which helps organizations manage, control and track requirements throughout the entire FPGA/ASIC development lifecycle by streamlining and automating the requirements engineering process such as capture, traceability, requirements versions tracking, results management and reporting. The new product is targeted for use in safety-critical industries in which rigorous certification standards exist, such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear.

Louie De Luna, Aldec DO-254 Program Manager, is quoted in the Press Release: “Ensuring that traceability exists throughout the entire development lifecycle is crucial to proving that the product has been designed and tested through a requirements-based process, from top-level design requirements to HDL source code, and from verification test cases to the testbench and through to the simulation results. Spec-TRACER is exactly what the avionics industry needs to help satisfy the traceability objectives of DO-254.”


pre-DAC 2013: TSMC certifies ATopTech, CDNS, MENT, SNPS

Thursday, May 30th, 2013


In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.

At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.

In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”

It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.


S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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