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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.

Paul Estrada: BDA with an ACE up its sleeve

 
May 23rd, 2013 by Peggy Aycinena

BDA chief operating office Paul Estrada has been at Berkeley Design Automation for over 7 years and is as enthused about the company today as when he first arrived. Particularly, because he says BDA is getting more attention than ever these days thanks to its growing portfolio of leading-edge products.

“We are a small business that continues to grow,” Estrada says with pride, “focusing on nanometer verification, a market where there are lots of problems, but where we are definitely making [inroads]. It’s an area that’s ripe for innovation, and better tooling, and as we don’t see the big EDA companies putting time or effort into making progress there, it’s a sweet spot in the market for us.”

Sounds great, so what’s the elevator pitch for potential customers?

Estrada responds easily: “Many companies continue to buy from our competition – principally Cadence and Synopsys – but we go into leading edge RF and analog/mixed-signal design teams and ask them what they can’t do with their current tools. They tell us and then we do those things for them with our tools. As a result, they buy even more tools from us and we go on from there.

“Clearly, the technical problems today are tough, but we know our customers solve them a lot easier and faster and better using our tools. And at some point in the process of comparing our tools with offerings from the big vendors, many customers end up using ours for more mainstream designs. Of course, they always start up with us first as they head into their leading-edge designs.”

Because there’s no innovation in the big EDA companies to support leading-edge designs?

Estrada, whose CV includes stints at Cadence, Synopsys, and co-founding O-In Design Automation later purchased by Mentor, has seen it all: “I worked in the biggest EDA companies back at a time when they were not nearly as big as they are now. Back then and even today, yes, innovation happens at those companies.

“However, getting really strong, new point tools through the process of innovation, development, ramp-up, successful customer engagement, and then changing how a design team works over time and migrates from what they’re currently doing – that process doesn’t do very well in the big companies. Certainly there’s lots and lots of innovation in those companies, but it doesn’t come to long-term fruition in many cases.”

So how does that process work at BDA?

Estrada says, “Our process is pretty straightforward. We ask design teams, the leading-edge guys, to tell us what they need and we usually hear that it’s a lot harder than what their current tools can do. They’re always wanting to do practical things that are just out of reach, and they have plenty of problems like that.

“For instance, we often meet with teams who tell us they can’t do simulations, their designs are too big. But with our Analog FastSPICE simulator for RF and analog/mixed-signal verification, we offer 100x the capacity of any other simulator in the market. So in almost every customer case, we find circuits that we can simulate, ones that nobody else’s simulator [can handle].

“At BDA, we focus on things that run at the transistor level. It’s our core business to [provide solutions] in four areas: high-capacity, high-performance circuits; mixed-signal simulation; accurate device noise analysis – the only accurate noise-analysis tool in the world; and analog characterization. In all of these areas there are big problems, but our solutions are exceptional and [introduce] plenty of innovation.”

That’s a lot for a small company. How do you avoid over-extending, exceeding your bandwidth?

Estrada says, “It’s pretty basic. We look at what the potential market size might be [for a product], and then ask how that compares with our resources. If it looks to be a big market, the answer’s a no brainier for a company our size. And even if it’s only a pretty reasonable market, it’s still seen as a reasonable risk.

“Which that ties back to innovation in the big EDA companies. Frankly, it’s not rocket science. We can look at a problem out there that would bring in a few million dollars a year, something that would never make sense for Cadence or Synopsys to focus on, and know that for us it would represent good growth.”

If the problem you’re attempting to solve for a customer becomes too narrow, or too specific, does BDA run the risk of descending, or ascending, into being a service provider?

Estrada says, “That’s a good question. For a lot of small companies in the technology space, not just in EDA, it’s very tempting to go towards an opportunistic development for a friendly customer that wants attention. But we can’t do that. We need to clearly delineate between developing for a true market, a group of customers with common characteristics, and developing for a single customer.

“Of course, if there’s a customer that will pay for something [akin to services], we will provide it. But we never let our service business interfere with our product development. We’re not masquerading as product developers when we do services.”

Speaking of products, BDA recently announced a new tool?

Estrada explains, “When you’re working in the analog space, there’s a lot to be verified. We call this process the ‘characterization’ of a given circuit under all conditions the circuit can expect to see once implemented in silicon. Until now, design teams and individual designers have not had a very good way of doing this.

“It’s work that’s tedious, error prone, and not at all sexy. They don’t do nearly enough of it, and it’s particularly onerous without [access to] better tools because it involves running hundreds, or thousands, or tens of thousands of different variations of what operating conditions the circuit is likely to see.

“So many tests, they can’t bring themselves to do enough of it. Instead, they pick out the most likely scenario and only run those. Unfortunately, the scenarios they never get to are the ones that often lead to lots of problems in silicon.

“This is what our new tool ACE is there for. It’s been developed to make it really easy to set up the runs, to have really fast simulations – using our simulators, which are really good, or even somebody else’s – and then to mine the data to make it obvious to the designer how things are coming along. Again, it’s not rocket science.

And who’s the competition for ACE?

Estrada says, “Synopsys and Cadence. However, if you’re working in a Synopsys world, you don’t have a reasonable environment. And if you’re working in a Cadence world, they’re using ADE, something that’s fine for design set-up and simulation, but really cumbersome when used for characterization. Which again is why we developed ACE.”

Speaking of bandwidth, why didn’t Cadence do this first?

Estrada replies, “Well, they’ve tried doing it several time now, with their latest offering in the market being ADE XL. But it’s clunky and not obvious how to use it.

“And because it’s difficult and not obvious, people avoid using it. They avoiding doing as much as they should do, because it makes it very difficult for the designer to find out what happened. They can see some results, but to mine the data being generated is really tough, particularity as it’s ‘trapped’ in ADE.”

Given all of the work that’s not being done on designs, it seems likely a lot of faulty silicon is being shipped these days.

On the contrary, Estrada says, pragmatic engineering is saving the day: “It’s my belief that designers are over-designing like crazy because of all of this. There’s no real downside to cause them not to, particularly as the last thing you want is for your circuit to fail in silicon. So they do as much over-design as possible.

“Of course, they can’t get away with it if they’re not meeting the specs, so first they over-design, then they measure the results through simulation for the most problematic scenarios, then they whittle away until the over-design finally meets the specs. But even then, there’s still a lot of bloat left. The over-designed circuit is too big, or too power hungry, or both.

“Also, you get a lot of silicon re-spins due to the analog [portion of the design], wasting a lot of time and money, or you get silicon that’s underrated from a performance standpoint. So you’re either throwing stuff out, or you’re changing the spec after the fact.”

Is it such a big problem to change the spec?

Estrada acknowledges, “Yeah, it could be just a temporary problem: ‘Let’s take this product and throw it at a different application’.

“But part of what’s going on here, is that analog/mixed-signal designers are few and far between. They’re a very scarce resource, hard to find, and hard to keep. If you’re managing a group like that, you don’t want your designers doing a bunch of stuff that’s menial, manual labor. There’s a worry that if you continuously ask them to do that kind of work, you’ll lose them.”

But where are they going to go work where their new manager won’t also insist on design diligence?

Estrada says, “Managers knows their designers should be doing more characterization, but don’t want to. Managers also know they’re running risks, but they don’t want to touch their designers. If the designer says it’s too hard to do, they won’t do the work. So basically, managers deal with this problem by leaving it up to the designers, which fortunately for us is an opportunity.

Gosh, they sound like a bunch of prima donnas.

Estrada is quick to respond, “You said that, I didn’t. What I said is that with ACE we’ve made it much easier to do this work.”

And do you enjoy your work?

Estrada replies emphatically. “Yes! I work with great people internally and outside of the company, people with high integrity. We’re working on interesting problems, and things are always dynamic. What’s not to enjoy?”


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From the May 16th press release …

Berkeley Design Automation today announced the immediate availability of Analog Characterization Environment — a high-productivity system to ensure nanometer-scale analog and mixed-signal circuits meet rigorous design performance requirements. ACE provides an intuitive user interface to rapidly setup, launch, monitor, report, and visually analyze complex circuit characterization runs. ACE supports leading SPICE-compatible simulators, standard measure formats, and operates both as a standalone tool and integrated with the industry’s leading analog design environment.

ACE reads corner information from the PDK or the user’s analog design environment, and it supports measures in existing industry standard formats for facilitating specification analysis. Designers can drag-and-drop characterization objects to create complex nests in seconds, define multiple-test run matrices, launch and monitor jobs, visually analyze results, and generate hierarchical reports.

“Traditional approaches have simply not kept up with the increasing complexity of nanometer-scale circuit characterization requirements,” said Ravi Subramanian, President and CEO of Berkeley Design Automation. “ACE is specifically designed to enable today’s circuit designers to quickly, easily, and comprehensively characterize their nanometer analog and mixed-signal circuits to ensure silicon success. By automating the tedious and error-prone tasks, ACE enables designers to work on high-value design and verification tasks.”

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