Archive for May, 2013
Thursday, May 30th, 2013
** Aldec announced the launch of Spec-TRACER, which helps organizations manage, control and track requirements throughout the entire FPGA/ASIC development lifecycle by streamlining and automating the requirements engineering process such as capture, traceability, requirements versions tracking, results management and reporting. The new product is targeted for use in safety-critical industries in which rigorous certification standards exist, such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear.
Louie De Luna, Aldec DO-254 Program Manager, is quoted in the Press Release: “Ensuring that traceability exists throughout the entire development lifecycle is crucial to proving that the product has been designed and tested through a requirements-based process, from top-level design requirements to HDL source code, and from verification test cases to the testbench and through to the simulation results. Spec-TRACER is exactly what the avionics industry needs to help satisfy the traceability objectives of DO-254.”
Thursday, May 30th, 2013
In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.
At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.
In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”
It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.
Thursday, May 23rd, 2013
BDA chief operating office Paul Estrada has been at Berkeley Design Automation for over 7 years and is as enthused about the company today as when he first arrived. Particularly, because he says BDA is getting more attention than ever these days thanks to its growing portfolio of leading-edge products.
“We are a small business that continues to grow,” Estrada says with pride, “focusing on nanometer verification, a market where there are lots of problems, but where we are definitely making [inroads]. It’s an area that’s ripe for innovation, and better tooling, and as we don’t see the big EDA companies putting time or effort into making progress there, it’s a sweet spot in the market for us.”
Sounds great, so what’s the elevator pitch for potential customers?
Estrada responds easily: “Many companies continue to buy from our competition – principally Cadence and Synopsys – but we go into leading edge RF and analog/mixed-signal design teams and ask them what they can’t do with their current tools. They tell us and then we do those things for them with our tools. As a result, they buy even more tools from us and we go on from there.
Thursday, May 23rd, 2013
ProximusDA has announced it’s working with STMicroelectronics to develop next-gen software virtual prototypes. ProximusDA brings its expertise in parallel-code distribution to the effort and STMicroelectronics knows a bunch about transaction-level modeling and distributed-computing architecture, so the combination’s terrific.
That’s according to ProximusDA CEO Enno Wein: “Our collaboration with ST demonstrates the beneficial synergy between ProximusDA and its customers. The first achievement of the collaboration has been to allow ST to build distributed execution runtime of its SystemC TLM platforms on machines with up to 64 cores.”
So what is it that ProximusDA is providing that ST finds so useful?
Thursday, May 16th, 2013
Let’s be honest. If you haven’t booked your flight and hotel yet for the Design Automation Conference in Austin in the first week of June, you’ve probably decided you’re not going. If that’s the case, more’s the pity because the sessions alone are going to be great, above and beyond the parties and networking, and will make the trip totally worthwhile. Here’s a sampling of the some of the topics that will be among the most compelling, with an acknowledgment that not everybody’s interests are the same.
Thursday, May 16th, 2013
Privately-held Calypto is on quite a clip these days, with developments at the company being closely followed by the press. That’s not completely surprising given that a new CEO came on board earlier this year, Sanjiv Kaul, and a new VP of Applications Engineering was named just this week, Thomas Bollaert being promoted into that role. I had a chance to speak with CEO Kaul recently. Following is a snapshot of that conversation.
Wednesday, May 15th, 2013
Not all of the 1600+ people who attended DATE 2013 earlier this year in Grenoble were able to fit into the room where the panel celebrating 30+ years of the Mead-Conway VLSI Revolution took place. Those who could, however, were treated to a lively 90 minutes of conversation on what that revolution meant to the world of electronics and chip design.
Organized by Synopsys’ Marco Casale-Rossi and moderated by U.C. Berkeley’s Alberto Sangiovanni-Vincentelli, panelists included Berkeley’s Jan Rabaey, IMEC’s Hugo de Man, CMP’s Bernard Courtois, Columbia University’s Luca Carloni, and Synopsys’ Antun Domic.
Although I was among those disappointed to have missed the event, I was able to speak after the fact with Antun Domic. He described the ambiance of the SRO session in Grenoble and enumerated several of the points laid out by the panelists, starting with their praise of Lynn Conway and Carver Mead’s ground breaking text book, published in 1980, Introduction to VLSI Systems.
Thursday, May 9th, 2013
Declaring itself open for business this week, Sage Design Automation wants to make the world a better place: a) by providing automated design rule closure for advanced process nodes, and b) by lowering the barrier for and broadening the use of design-rule based checking, beyond foundry-provided rules, with a user-friendly GUI.
Speaking by phone with company CEO Coby Zelnik, previously CEO of Sagantec, I found he’s very jazzed about the new company and what it portends for the future. To explain Sage, he offered a brief history of things up to this point:
“Historically, there have been a lot of challenges in physical verification. In the last 20 years, it’s always been about speed of the tool and what size of chip it can process, and so on. All of these vendors were competing on how fast they could run DRC on the biggest chips. But nowadays, these tools can utilize, tens, hundreds, or even thousands of CPUs to get things done well, so there’s no more bottleneck there.
Thursday, May 2nd, 2013
Wednesday night, at the outset of the EDAC Jim Hogan/Joe Costello event, the DAC 2013 General Chair, Synopsys’ Yervant Zorian, took the stage to present a plethora of reasons why you should be coming to DAC in Austin in June. Here’s his list in the order in which it was presented:
No. 7 – When the DAC Executive Committee went looking for Austin-based EDA folks to assist in connecting the design community in Texas to the folks who plan DAC, the EC expected 3 or 4 persons to respond. Instead, over 35 people raised their hands and hence the Austin-based DAC committee is huge and has done a great job.
Wednesday, May 1st, 2013
Joe Costello came to town tonight and wowed his acolytes.
Thanks to EDAC, Kathryn Kranen, Steve Pollock, Bob Gardner, Jennifer Cermak, Jill Jacobs, Gloria Nichols, and Cadence – Jim Hogan hosted Costello on stage at Cadence’s San Jose Headquarters for a 90-minute event that was one part Reunion Tour [lotsa Cadence alums in the audience in addition to the two on stage], one part Pity Party for Mentor Joe & Mentor Jim [oh so many visits to VCs who failed to embrace a startup’s pitch], and one part Brag Fest for VC Joe & VC Jim [oh so many visits from potential startups whose pitch we simply could not embrace].
Add up those parts and you’ve still only got half of the content of tonight’s event; the other half of the Joe Costello Love-in consisted of a detailed Lesson in Rhetoric. Perhaps not surprising, given that the event was titled: Joe Costello Shares His Secrets for Communicating a Compelling Company Story. What is surprising is how closely Costello’s advice to his adoring audience mirrored Cicero’s Five Canons of Rhetoric.