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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Vertigo: funFITs or fudFITs into finFETS?

March 28th, 2013 by Peggy Aycinena

To say this is the year of the finFET is somewhat of an understatement, because everywhere you go somebody’s talking about going up instead of out – at ISSCC, at DesignCon, at DVCon, at ISQED, at SNUG, at EDPS, at DAC.

Among the talks so far, one of the best was given by the father of the finFET himself, U.C. Berkeley’s Chenming Hu. If you were at ISQED in Santa Clara on March 5th, you heard Prof. Hu describe how increasing leakage current in planar devices motivated radical new thinking in the late 1990s: Instead of a classic source, drain, gate structure, take a thin film of high-quality silicon material, place gate-dielectric above and below it such that the silicon is never very far from the gate, and then turn the thing 90 degrees so that the source is out the back, the drain’s in front, and the gate material is vertical.

According to Prof. Hu, the result was something that looked like the back fin of a fish – a finFET – and was a concept that spawned a decade’s worth of additional research, innovations, and re-energized optimism with regards to device scaling. In other words, if your idea of fun is the unabated March of Moore’s Law, the finFET has emerged as the thing you’re looking for.

Before you begin to celebrate, however, consider the implications of a keynote delivered this week at the Synopsys Users Group conference in Silicon Valley. Wednesday morning’s featured speaker was TSMC VP of R&D Cliff Hou. At first listen, his talk seemed a straightforward showcasing of the benefits versus the challenges of finFET technology.

After a while, however, Dr. Hou’s laundry list of what EDA vendors still need to provide to make finFETs a reality seemed to showcase instead a growing sense of fear, uncertainty and doubt, his list casting a shadow over the near-term potential for the technology and making the sunny messaging of Prof. Hu way back at ISQED hard to recall.

After articulating the benefits – lower leakage, higher driving current, low-voltage operabiltiy, better mismatch, and higher intrinsic gain – Dr. Hou said making finFETs a full-on reality will require EDA vendors to provide a host of complex solutions – tools for parasitic RC extraction, tools for EM reliability and power integrity, design methodologies for low-voltage operability, design methodologies for interconnect resistance minimization, as well as a hearty array of improved device and circuit models. All told, an almost-impossible-to-deliver tool kit.

After laying out the list, however, Dr. Hou changed his tone and said TSMC has the solution in hand today for everybody’s problems. He said the company is masterful at orchestrating collaboration across its global ecosystem of tool partners, IP partners, and design partners – and those guys working under TSMC’s guidance have got the situation under control. Nobody should worry. The future is bright because TSMC is “unleashing innovation that’s improving the quality of life.”

Very confusing, very surrealistic, very Hitchcock. One minute you’re fine, next minute you’re confused. One minute finFETs are fun, the next minute they’re terrifying. One minute, the tools needed to design finFETs are not here. The next minute, the manufacturing needed to implement them is moving forward at an astonishing clip.

Thinking about finFETs? Thinking about going up instead of out?

Think about Vertigo. Be very afraid of heights.


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