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Archive for February 21st, 2013

Verific Design Automation: Standing tall

Thursday, February 21st, 2013

 

If you’re in EDA and haven’t heard of Verific Design Automation, it would appear you haven’t been listening. Michiel Ligthart, Verific President and COO, told me in a recent phone call that few people in the industry are unaware of his company’s offerings: “We’re very well known in the industry. Everybody who works in EDA knows us, or if they don’t, we are no more than 2 or 3 phone calls away.

Verific is a little bit different kind of company. We are a small solutions providers, but we do not have an end-user product. Instead, we provide SystemVerilog and VHDL parsers that we license to EDA companies, and to semiconductor companies that build EDA products for internal use or for their customers.”

I asked why such companies don’t build their own parsers, and he said, “In fact, they could. These are based on IEEE standards and anyone could build them, but the parsers must be the same for everyone. If you can buy them from somebody else, rather than build them, it means you can concentrate on your distinctive solutions. Verilog parsers from companies like Cadence or Synopsys all have to adhere to the same standard.”

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DVCon 2013: There is such a thing as a free lunch!

Thursday, February 21st, 2013

 

You may think it’s a cliché, but it turns out there is such a thing as a free lunch at DVCon 2013 from February 25th to 28th at the DoubleTree in Santa Clara.

If you attend all 4 days of the conference, you will be the guest of the Accellera Systems Initiative, Mentor Graphics, Cadence, and Synopsys on Monday, Tuesday, Wednesday, and Thursday, respectively. More important than the food, however, is the exposure to the learning — albeit with a heavy dollop of company messaging on top. You should be there.

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