Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at www.aycinena.com. She can be reached at peggy at aycinena dot com.
Master & Commander: DVCon’s Stan Krolikoski
February 6th, 2013 by Peggy Aycinena
Now in its 25th year, DVCon is coming up in a couple of weeks in Silicon Valley. In terms of process nodes, 25 years is about twelve generations. In terms of dog years, it’s about four generations. In terms of the life of Stan Krolikoski, however, 25 years is only part of one career. It’s also the amount of time Stan’s been going to DVCon, even though it had a different name when he attended the first such conference back in 1988.
When I spoke with Stan by phone earlier this week, I asked if he’s been to every single conference since then. He laughed and said, “Absolutely! Looking back to 1988 – despite all of the mergers, and the coming together of various conferences, and the end of the HDL wars – I’ve been to every one of them!”
There’s nobody else who’s been to them all? Stan laughed again, “I don’t think so. They’ve either retired, or left the industry. Although I do think Dennis Brophy has been coming for a long time, but probably not all the way back to the beginning.”
Where was the first conference held in 1988? Stan said, “It was in Newport Beach. Why? Who knows. Back in the day, a number of meetings were held in Newport Beach. Maybe it was a destination, or maybe it was because there were a lot of defense contractors in the area. Remember that VHDL-87 had just come out and the language had a connection to the Department of Defense.”
Soon after VHDL was introduced, Stan noted, Verilog was introduced and the competition between the two languages, and their respective conferences, was on. The VHDL International User Forum, VIUF, began in 1991, and the International Verilog Conference, IVC, began in 1993.
VIUF and IVC were dueling conferences that represented the duality and war between the two language camps, VHDL and Verilog. Stan said, “After a number of years, the two conferences joined in 1997 to become IVC/VIUF, admittedly a pretty unwieldy name.
“By the end of the 1990’s, however, IVC/VIUF evolved to become HDLCon, a direct result of the end of the language wars. And then in 2003, HDLCon became DVCon and the current conference was born.”
I asked Stan if this year is the first time he’s been Chair. “Yes, for DVCon,” he said. “But back in the day, I was in charge of several of the precursor meetings. Of course, I’ve been involved with the current version, DVCon, for a long time.
“I’ve been doing the Program Committee for four or five years, and before that was Tutorial Chair. I’ve also run the Town Hall Lunch on Mondays. And this year, with Karen Bartleson taking off to the IEEE [she’s currently serving as President of the IEEE Standards Association], I was next in line. I’m General Chair this year, and will do the job again next year.”
With so much history to the conference, how is Stan hoping to leave his stamp on things these several years? He said, “Well, it all started as HDL conferences with people wanting to know how to do various statements, and how to make the languages work together.
“Then, around the beginning of the millennium, about the time when DVCon took over from HDLCon, the focus became more on the user experience and not so much on the languages themselves. And, people started to have to worry about SystemVerilong, and how do users use these new languages.
“For example, during the Accellera Day on Monday this year, when we look at standards, we’ll be looking at UVM [Universal Verification Methodology]. But instead of just giving a tutorial about UVM, the focus is going to be on how the users are deploying it, now that they know it’s there. And, a number of paper sessions this year will include case studies using the methodologies and the standards, as opposed to just talking about how the languages fit together.
“When I came up in 1988, I was at Honeywell, and eventually moved to IBM before coming over to the dark side into EDA. I know and understand how users can get lost in the morass of languages. It’s important to me, and the whole committee, to know that users coming to DVCon will learn stuff they can actually use on their jobs. That’s why users come to this conference in droves.”
Droves? Isn’t DVCon a small boutique conference in comparison, say, to DAC? Stan replied, “DAC covers a much larger territory, all the way from the system down to the silicon. At DVCon, however, we focus on the front end, design and verification.
“And actually, we’re not that small. We had 800 people last year, which makes us pretty good sized. In fact, over the last couple of years – even in the face of a major recession – we’ve gone from three days to four days, from four tutorials to ten tutorials, and have expanded from just paper sessions to including poster sessions as well. Overall, we’re really growing.
“We’re part of the industry, and an important part. The bottom line for DVCon? I’ve always liked that you could actually sit down and talk with your professional colleagues.
“DAC is hectic, and if I’m a vendor there it’s always the push to get yet another group of people into the booth. But DVCon is different. I’ve always found that my favorite times at DVCon is when I can sit down with two or three colleagues for some real conversation.”
I asked Stan to tread dangerous waters: What are you looking forward to the most at DVCon this year?
He said, “Well, if I have to point to some of the highlights, I’d have to say that the first day, Accellera Day, is going to be excellent. The group that represents the merger of Accellera and OSCI, Accellera Systems Initiative, is sponsoring the event, which will highlight UPF [IEEE 1801 Unified Power Format], and include tutorials on analog/mixed-signal verification, SystemC, and migrating to UVM.
“Monday will actually include four tutorials sandwiched on top of the Town Hall Lunch where attendees will have an open forum where any and all questions can be asked. Monday’s going to be a really great opening to a week where people will be able to learn a lot.
“On Tuesday, Wally Rhines is giving the keynote and he’s always excellent. And the paper sessions all week will offer in-depth discussions, as always, but also the poster sessions are going to be very good. At a lot of conferences, the poster sessions are lonely affairs with presenters waiting for people to come ask questions. At DVCon, we’ve changed that. We’ve worked to guarantee that the poster sessions are not the bastard child at DVCon.
“For every paper proposal to DVCon, some became papers and some became posters. We see the poster sessions now as an opportunity for users to get up close and personal with the presenters – people that often have many years of experience in the field – and not just a session with 300 of your closest friends looking at PowerPoint slides.
“Finally, on Wednesday, we have bookend panels. In the morning, they’ll be looking at where design ends and verification begins. That session has been organized by Graham Bell and has a good group of presenters.
“In the afternoon, JL Gray’s Industry Leaders Panel is titled, To 1 Million Design Starts. A lot of people want to get their ideas into silicon, but the costs are prohibitive. JL’s group is going to talk about the barriers for both small and large companies to continue innovating. Yervant Zorian from Synopsys, Serge Leef from Mentor, Ziv Binyamini from Cadence, Sunil Shenoy from Intel, and John Costello from Altera will be on that panel.
“But really, the whole conference is going to be excellent. As Chair of DVCon, I wanted to make sure that everyone who attends comes away knowing something new. The DVCon committee has put together a great conference, and I’m confident this is going to happen.”
Stan Krolikoski has been deeply involved in standards activities throughout his 25+ year career in the EDA industry. He is currently Distinguished Engineer at Cadence Design Systems. Dr. Krolikoski has previously worked for ChipVision Design Systems as CEO, Cadence as Senior Architect and VP of Marketing, Compass Design Automation as Senior Fellow and Chief Technologist, and CLSI as VP of Engineering. He holds a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign and a second Ph.D. in Philosophy from the same university. He also holds a Philosophy degree from the University of Leuven in Belgium.
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