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Editor’s Notebook: ISSCC Mobs, Flash, and Dash

Wednesday, February 22nd, 2012

 

This week, a mob of more than 3000 people from all over the world has packed into the subterranean conference space of the San Francisco Marriott Hotel to attend ISSCC 2012, the 55th annual IEEE International Solid State Circuits Conference.

Getting there in time for the opening keynotes first thing Monday morning was easy – no traffic, thanks to the Presidents Day Holiday – but once you came down the escalators into the bowels of the Marriott, it was a total zoo. Of course, ISSCC always is.

As the granddaddy of all solid state conferences, it’s the place where some of the most historic circuit design announcements have been made over the years. Everybody wants to be there, and this past Monday nobody appeared to regret not having the day off – particularly during the plenary session when the cavernous hall was filled with thousands of people sitting in countless tidy rows, stretching off into the darkness. Even the keynote speakers commented on the impact of looking out across that sea of people. Yeah, ISSCC is really something.

This year’s keynotes included SanDisk co-founder Eli Harari talking about the history of Flash, a technology he said is now both ubiquitous and unstoppable, and well on its way to eliminating HDDs in its meteoric rise to success fueling the consumer electronics industry.

STMicro Senior EVP Carmelo Papa spoke of a critical synergy between energy consumption and semiconductors: More people and bigger cities in the coming decades will exceed all power utility capacity, he said, unless smart chips, bodies, homes, grids, and governments build together on the efficiencies and intelligent promise of IC-based systems.

In a similar vein, Renesas EVP Yoichi Yano promised MCUs, in combination with Flash, will ease a plethora of power-demand problems and will go a long way to making the world green, at last.

Finally,  Intel EVP David Perlmutter gave an emotion-packed keynote that laid out strategies for optimizing transistor-level power consumption, invoking all the usual suspects – smaller process technologies, 3D stacking, and heterogeneous multi-core devices. Perlmutter’s address was as close as it comes to a rousing stump speech and call to action for the uber-nerds of the semiconductor industry. It was fabulous.

Between keynotes, major awards were presented at ISSCC on Monday morning. Of interest to those in EDA, stalwart industry legend Ron Rohrer received the 2012 Gustav Kirchhoff Award, and UCLA’s Behzad Razavi received the 2012 Donald O. Pederson Award. Those who know Rohrer would not be surprised to learn that when he stepped to the podium to thank the IEEE, he first acknowledged SPICE-collaborator Larry Nagler, and then got a huge roar of laughter from the enormous audience when he admitted that Kirchhoff’s Laws are the only laws he has managed to obey throughout his life.

During a break in the 4-hour plenary session marathon, I dashed into the Press Room for a cup of coffee, a carb, and a chance to catch up with various colleagues. Dave Bursky was there – busy with his new enterprise, PRN Engineering Services, and continuing to astound by attending more conferences per week than anyone else in the industry.

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Pop Quiz: The Standards Game

Friday, February 17th, 2012

 

Here’s your February Pop Quiz.

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1 – DVCon 2012 starts on February 27th. The conference was first held in _____.

a) 1989
b) 1995
c) 1998
d) 2003

2 – The IEEE Standards Association [IEEE-SA] oversees approximately _____ standards and _____ standards under development.

a) 500, 900
b) 800, 600
c) 900, 500
d) 700, 900

3 – The IEEE Standard associated with VHDL is _____.

a) IEEE Std 1064
b) IEEE Std 1076
c) IEEE Std 1164
d) IEEE Std 1176

4 – Accellera merged with _____ in 2011.

a) VSIA
b) OSCI
c) OCP-IP
d) OVI

5 – DVCon is managed by MP Associates, the same group that manages _____.

a) ICCAD
b) DesignCon
c) Semicon
d) ISQED

6 – The 2007 General Chair of DVCon was _____.

a) Tom Fitzpatrick
b) Stephen Bailey
c) Shankar Hemmady
d) Gabe Moretti

7 – SystemVerilog was donated to Accellera in _____.

a) 2000
b) 2001
c) 2002
d) 2003

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The Cloud: It’s Not Who You Know

Tuesday, February 14th, 2012

 

Thousands of people are in the Santa Clara Convention Center this week for Cloud Connect 2012, and I don’t know any of them. They’re all in IT, and apparently those people don’t overlap with EDA people.

After spending several hours in the Exhibit Hall this afternoon, talking to folks in booths and in hallways, the only person I found was a guy in a Big Company booth who told me his wife used to work for Synopsys, and before that for Cadence. He knew a lot about SalesForce and financial services, but that’s not exactly like knowing how EDA’s needs are being met in the Cloud.

So why go to the conference? For one, the Cloud’s got a lot of buzz, and the issues are fascinating and complex. And for two, chip design is really compute intensive and requires a lot of data be manipulated, stored, and shuttled from here to there. Doing chip design in the Cloud is a natural fit, and if the designs are going to be done out there, the EDA tools have got to be out there as well. But are they?

You and I both know they are, and so do the CAD Managers in the Big Design organizations, as well as the Cloud Managers in the Big EDA organizations. Just because I didn’t run into those people at Cloud Connect, doesn’t mean they don’t exist. They do indeed exist, and they’re damn busy dealing with all of the issues I heard discussed today in the Exhibit Hall, in the morning’s keynote, and in the afternoon’s technical sessions.

Those issues include – figuring out when it’s time to migrate some or all of your engineering apps to the Cloud, figuring out if your Cloud’s going to be private, public, or a hybrid of both, figuring out which consulting services are best suited to help you with the process of getting everything up there, and then figuring how much all of that’s going to cost.

Then there’s figuring out which web service provider should be hosting your data and data crunching, and figuring out if the latency issues that result from designing in the Cloud will, or will not, outweigh the benefits of access to enhanced on-demand compute & storage capacity and reduced IT infrastructure costs.

There are also issues related to disaster recovery. The presumption must be that outages will occur. It can’t be about MTBF, per Opscode’s Jesse Robbins. It’s got to be about MTTR, Mean Time To Recovery. What are you going to do when your web service provider goes dark?

Oh yeah, and there’s one other thing, the issue that swamps all of the rest of them combined – security. How do you keep your design secure as it evolves, if the process is being hosted on a server outside your firewall? And if you’re an EDA vendor, how can you guarantee that your tools are safe out there, protected from both piracy and attack?

Well, from what I heard today, you actually can’t. You can’t keep your design secure, and you can’t protect the tools from piracy and/or attack – at least not 100% – and it’s learning that which made my trip to Cloud Connect worthwhile.

Even though they were reluctant to admit it, there wasn’t a single person I met today who claimed that security on the Cloud is a done deal, that it’s as secure as keeping designs, tools, data – stuff in general – on your own rack of servers, in your own cozy data center, nice and safe and sound inside your own impenetrable firewall. And that’s the reality of the State of the Cloud here in 2012.

It’s not who you know in the Cloud. It’s who you don’t know. They’re the ones who want to steal what you’ve got, bust what you’ve got, or just mess around with what you’ve got merely for the reason that Evil is Real. Here on Earth, and up there in the Cloud.

So, deal with it. Figure out how to make things 99.99% secure with all of the strategies already underway – protocols, encryptions, and most amusingly, getting your web service provider to promise they’re working to the latest industry standards – and then accept the fact that the Cloud is here to stay.

As Geva Perry said in his Cloud Connect keynote, CIOs everywhere are trying to keep their employees from migrating to the Cloud without permissions. However, Perry said, the employees are already out there, so work with them and help them make the move to the Cloud happen in as secure a way as possible. Deal with it.

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DVCon: You will be Tested

Friday, February 10th, 2012

 

Pay close attention. You will be tested on the following.

DVCon stands for Design & Verification Conference. Not surprisingly, it’s targeted at design and verification engineers. Despite rumors on the street, design and verification engineers are still two different types of employees, particularly at the big design houses. That’s why DVCon is applicable to both. Two disciplines. One conference.

DVCon happens every year around this time at the Double Tree Inn in San Jose. Approximately 700 people attend. The conference is 4 days long, including 2 days of tutorials on either side of 2 days of technical sessions. There’s always one major panel, this year on February 28th, that showcases industry execs. Famously, it used to be moderated by John Cooley. Now it’s moderated by JL Gray, who is also famous.

JL’s panel this year will include Ted Vucurevich, John  Costello (sic erat scriptum), Gary Smith, and Jim Hogan. If you do not know who these people are, perhaps you should not be coming to DVCon. Unless you’re a design or verification engineer, in which case that’s okay. You’ll probably know someone on the panel the next day hosted by Brian Bailey, who is not famous. He is legendary. Brian’s panel is about Hardware-Assisted Verification and includes people from Qualcomm, ARM, SpringSoft, Xilinx, and Cadence.

DVCon also has a major keynote, this year on February 29th, which features the CEO of one of the Big 3 EDA companies. Last year it was Mentor’s Wally Rhines. This year it’s Synopsys’ Aart de Geus. His talk is entitled: Principles for Success in IC Design. DVCon is well known for this type of positive thinking. Last year, JL Gray’s panel was entitled: Making Great Products Great. This year it’s entitled: The Resurgence of Chip Design. You will not find a keynote at DVCon entitled: Principles for Failure in IC Design, nor a panel entitled: Making Great Products Lousy. That kind of thinking is not what DVCon is all about.

DVCon is sponsored these days by Accellera Systems Initiative, a single organization created last year out of two separate organizations, Accellera and OSCI. That’s because both organizations are interested in system-level design. NASCUG is also interested in system-level design. It too has a presence at DVCon. If you don’t know what NASCUG means, click here. Meanwhile, remember that Accellera was itself created in 2000 out of two separate organizations, OVI and VHDL International. This type of thing is also what DVCon is all about. People helping people make their organizations better. People helping people figure out how we can all get along.

Creating standards is another way of figuring out how we can all get along. Which brings us to Karen Bartleson. Like Accellera Systems Initiative, Bartleson is a single person who represents two complementary ideas: Standards and Positive Thinking. This is why Karen is the perfect person to be General Chair of DVCon. She is Synopsys’ go-to person for all things related to Standards, and she is nothing, if not all about Positive Thinking. Add these together, and multiply by two, and you see why this is the second year in a row that Karen has been DVCon General Chair.

Karen will not be General Chair next year. She will be busy doing something else. She will be serving as President of the IEEE Standards Association, overseeing 900 different standards and the 15,000 people who maintain and update those standards. Maybe she could invite all of those people to DVCon in 2013, although it might get a little crowded if they all came. MP Associates, the folks who run DVCon (and DAC among other things), might run out of conference bags. Nonetheless, MP Associates is a very capable organization. If Karen Bartleson got all 15,000 IEEE standards committee members to come to DVCon next year, I’m sure that MP Associates would be up to the task.

Speaking of people who like people, that brings us to the idea of networking, wine/beer, and exhibit halls. DVCon serves up a generous dollop of all three, along with the tutorials, keynotes, panels, and technical sessions. I have checked with Karen Bartleson and she assures me that when the DVCon 2012 Exhibit Hall is open – February 28th from 3:30 to 6:30 pm, and February 29th from 4:00 to 7:00 pm – there will be lots of networking, food, wine/beer, and sanctioned recruiting amidst the 30+ exhibitor booths.

She also emphasized that the wine/beer will be complementary to all attendees. That might be a tall order for next year if 15,000 people come to DVCon. All the more reason why you should be planning to come this year. Serving up wine and hors d’oeuvres to 700 people is an order of magnitude easier than serving same to 15,000. Even if highly capable MP Associates could pull it off. Or if DVCon organizers could afford it.

Speaking of money, DVCon is good there as well. They have made enough money to be profitable several years in a row. Accellera Systems Initiative, apparently, also has some extra money because they will be presenting a monetary award to the Best Paper winners at DVCon. Yet another reason to attend. The Best Paper selection will be done by the attendees themselves, voting throughout the conference to determine who will be announced Big Winner in the last session on February 29th. Karen said receiving Best Paper at DVCon is something special, particularly given the quality of the papers submitted.

Okay, if you’ve read carefully to this point, there’s only three things left to do.

* Register for DVCon.

* Watch Karen Bartleson’s upcoming Conversation Central interview with the DVCon 2012 Technical Program Chair and Tutorials & Panel Chair on February 16th.

* Take the quiz, which will be posted here on February 17th.

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Marcy: The Hunt for Other Worlds

Wednesday, February 8th, 2012
 
 
U.C. Berkeley Astronomy professor Geoff Marcy spoke to the San Mateo County Astronomical Society on the campus of the College of San Mateo last Friday evening, February 3rd.
 
Marcy’s been a Science Celeb since 1996 when he was featured in Time Magazine, along with Paul Butler, because of their work which identified a planet not dis-similar to our Jupiter circling a star named 55 Cancri, a discovery that offered hope there might be an Earth-like exo-planet in that neighborhood as well.
 
Now, 16 years later Marcy and collegues are grabbing headlines again. This time it’s based on their recent announcements that several exo-planets much closer to the size of our Earth have now been ‘directly’ observed by NASA’s Kepler Telescope.
 
Launched in March 2009, and operated by NASA Ames Research Center, Kepler orbits around our sun in an Earth-trailing orbit that yields a super-unimpeded view of the universe.
 
Marcy told his audience last Friday that Kepler has revealed “lots of planets” in its brief lifetime, over 2300 planets residing in 170 different planetary systems within that fraction of sky the telescope’s been peering into with its unblinking 1-meter parabolic mirror for almost 3 years – a 10-degrees-squared viewing area near Cygnas with 150,000+ stars visible therein.
 
The team at U.C. Berkeley, in conjunction with NASA and the Keck Observatory in Hawaii [operated by UCB], has seen each of these 2300+ planets by tracking the periodic dimming of its associated star – from very bright to 99.99% as bright – as the planet passes into the line of sight between Kepler’s ‘eye’ and the star under observation.
 
Marcy said, “We ascertain the planet’s presence and size by the periodic drop in brightness of the star its orbiting.”
 
Of course, planets that don’t happen to traverse that line of sight would not be seen, and neither would planets that haven’t passed by in the last 3 years since Kepler’s been looking.
 
Marcy acknowledged that those “objects of interest” probably make up the bulk of the hypothetical planet population: “We’re undoubtedly missing 99 percent of the planets. Nonetheless,” he said multiple times, “it’s an extraordinary moment in history!”
 
Particularly because last December’s announcement from the Kepler-Keck team that several planets as small as 2x Earth’s radius were observed, has now been eclipsed by the team’s subsequent announcement that two planets approximately the same size of Earth have now been spotted – albeit, whipping around star Kepler 20 at a pace that would rip you and me apart at the seams, with orbital transit times of a breathtaking 6.1 and 19.6 days, respectively!
 
Okay, Marcy acknowledged, so these places aren’t exactly habitable. Planets Kepler 20e and Kepler 20f are too close to their sun, hotter than Hades, with surface temps exceeding 2000 degrees C, and of calculated densities [based on size and orbital period] that preclude the existence of water – but the hunt has just begun, and the significance of what Kepler’s seen so far is totally profound.
 
Marcy said the Apollo Moon landing, the sequencing of the Human Genome, and the first sightings of Earth-sized planets are all massive milestones in human history, with this last perhaps being the greatest, because we may be on the verge of finding habitable Earth-like planets – ones that reside in the legendary Goldilocks Zone.
 
And why does that matter?
 
Well, apparently we’re lonely here on Planet Earth and can’t wait to find other life forms living outside of our own puny sphere of existence. Or, we’re killing our current Earth and need to trade it in for a cleaner model.
 
Either way, this is the stuff of dreams – the stuff that drives Sci-fi enthusiasts, amateur astronomers, and uber-nerds to spend Friday nights hanging out in the lecture hall. After his talk, Dr. Marcy happily answered questions from all of them.
 
 

Malapropism: Like Apples and Oranges

Thursday, February 2nd, 2012

As Facebook’s IPO promises at last to move from carrot to stick, let’s take stock of several companies, also working out of Silicon Valley, that make the hardware possible that the leviathan FB sits on. We’ll start with Synopsys.

Synopsys was founded in 1986, went public in 1992, and currently has 6800 employees. According to the company’s November 2011 announcement, Synopsys earned $221.4 million on fiscal 2011 revenues of $1.536 billion, roughly $226 thousand of revenue per employee. Shares of SNPS are up about 8% in the last 12 months, setting the present market cap at $4.28 billion. Now let’s look at Cadence.

Cadence was founded in 1982, went public in 1987 [as ECAD], and currently has 4600 employees. According to the company’s February 2012 announcement, Cadence earned $72 million on fiscal 2011 revenues of $1.150 billion, roughly $225 thousand per employee. Shares of CDNS are up about 23% in the past 12 months, setting the present market cap at $3.17 billion. Now let’s look at Mentor Graphics.

Mentor was founded in 1981, went public in 1988, and currently has 4700 employees. According to Yahoo Financials, Mentor earned $77 million on fiscal 2011 revenues of $1 billion, roughly $217 thousand per employee. Shares of MENT are up about 11% in the last 12 months, setting the present market cap at $1.57 billion. Now let’s look at Magma.

Magma was founded in 1997, went public in 2002, and currently has 700 employees. According to Yahoo Financials, Magma earned $5.3 million on fiscal 2011 revenues of $139 million, roughly $199 thousand per employee. Shares of LAVA are up about 27% in the last 12 month, setting the present market cap at $494 million. Synopsys announced last November that they intend to acquire Magma for $507 million. Now let’s return to Facebook.

Facebook was founded in 2004 and has around 3000 employees. According to the company’s just-released pre-IPO filing, Facebook earned $668 million on 2011 revenues of $3.7 billion, roughly $1.233 mllion per employee. Revenues in 2011 were up over 100% from 2010. Facebook is still privately held, but estimates put the post-IPO market cap at around $100 billion. Famously, the founder dropped out of college, is currently 27, and may soon be worth about $28 billion if investors’ dreams of IPO glory are fully realized.

So let’s think about this, even if at the risk of comparing apples and oranges. How is it that a company like Facebook (started by a guy who doesn’t even have an A.A.), from a revenue and growth perspective is beating the pants off of a suave consortium of Ph.D.s and techno-visionaries, those EDA guys who pride themselves on grasping and advancing the most complex concepts at the interface between hardware and software design, not to mention the business models that support it all? Why aren’t these highly educated/polished EDA guys all worth billions? (Albeit, several may be, but it’s not based of their winnings in EDA.)

Let’s see: Facebook is young, edgy, loose, and unorthodox – or at least, it likes to be seen that way. EDA is many things, but it’s neither edgy nor unorthodox. FB was rolled out across a cascading hierarchy of markets, and now appeals to a vast range of demographics. Nope, that ain’t EDA either. And FB’s success has been piggy-backed on the hottest consumer products of the last decade: smart phones, digital cameras, and streaming everything. Now here, FB and EDA have something in common. All that hardware that FB lives on has come to fruition, in no small part, thanks to the likes of SNPS, CDNS, MENT, and LAVA. Kudos to EDA for that; too bad they don’t have the revenue to reflect it.

Final analysis? Facebook is everywhere and EDA is nowhere, when it comes to name recognition and  investor lust. As for an answer to the implied inequity in this equation, there isn’t one. EDA will continue to be a beast of burden for the consumer industry, and phenoms like Facebook that morph out of it, for the foreseeable future. EDA folks can either live with it, get out of the frying pan, or buy low, sell high.

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Peggy Aycinena is a freelance journalist and Editor of EDA Confidential [www.aycinena.com]. She can be reached at peggy at aycinena dot com.

Verific: SystemVerilog & VHDL Parsers



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