Blue Pearl: Facilitating FPGA design

Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.

Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.

“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.

“By adapting our Grey Cell methodology, IP providers can take their IP and give enough information for inter-IP analysis without exposing their secret sauce. From the input to the first flip-flop and from the last flip-flop to the output, only enough information is given to the user to make it possible to do better analysis of their clock domain crossing and multi-cycle paths.

“Most people need help with clock domain crossing, or at least have reliability issues with CDC in the field, since the number of clocks in designs is increasing rapidly. Having a Grey Cell helps integrate IP with a design’s RTL and supports inter-IP analysis. Then a designer doesn’t have to carry a lot of data for analysis and can do full-chip CDC analysis, which will [in turn] reduce reliability issues in the field.

“Multi-cycle path and false path analysis is also important and an extension of what we have been doing. Before, for each block of IP, people considered the IP to be a black box and could not do false path analysis. Now [our tool] gives the designer another level of detail that helps them create the SDC constraints to drive the efficiency of synthesis and place-and-route.”

Is Blue Pearl focused only on FPGAs, I asked.

Shakeel said, “Our tools work for both ASICs and FPGAs, but we see the growth in the use of FPGAs – especially in embedded systems – as a big plus for us. And since our tools are easy to use, the price point is right, and they work on Windows, this is very attractive to the FPGA market.”

Given this increased tool capability, how close are we to seeing FPGAs used as end products?

Shakeel said, “Actually, for 28-nanometer designs, production FPGAs are already in use. I just returned from Asia and that is certainly the route the Chinese are taking. They are quickly gearing up to design using FPGAs, and have been positioning themselves that way for the last year and a half. [Overall], the true ASIC market is diminishing and as the embedded market increases, there will definitely be FPGAs in there. In particular, linking FPGAs and DSPs together is a combination that is showing a lot of promise.”

And 10 years from now?

Shakeel said, “FPGAs definitely will be more important that ASICs. The power/area and programmability trade-offs will push feature sets back to the software and flexible hardware. Blue Pearl will support that process.”

Along with Adacsys, Blue Pearl made a joint presentation at SAME. Why?

Shakeel said, “That presentation at SAME was all about helping designers get their design into a position for hardware validation as soon as possible. Blue Pearl is involved in the front end, while Adacsys is in the back end. Our joint talk at SAME was about getting to the validation phase as quickly as possible. We talked about linting, using our tools for SDC generation, to check the design for a specific methodology, and a methodology flow that reduces design iterations – all tied to specific applications, things like military and transportation.

“Users of Altera and Xilinx spend a lot of time optimizing their designs for the vendor-specific devices, but they need to get their work done as early as possible. They want to accelerate getting to clean RTL, and want to quickly test the design on the board. Blue Pearl is involved in the RTL analysis phase, while Adacsys implements the design quickly on the board to verify the hardware.”

Isn’t that just emulation?

Shakeel said, “It is slightly different from traditional emulation. Here you’re doing binary implementation and you’re testing the board itself – testing the actual design on the board. An example might be an industrial application. You have your board, and you need to be able to verify that the board is compliant to a specific methodology.”

What specific methodologies are you referring to?

Shakeel said, “For industrial applications, there are a certain number of checks that need to be done – for example, the way you implement a global reset can be resource intensive, so you need to check how you’re implementing them in the design, so you’re not over using resources or implementing a function in too many levels of logic.

“If you’re making a decision tree, the way you code your RTL  is not be the same for an ASIC versus FPGA. Their implementation impact is very different. The check that you can do with our linking tools allows you to understand the impact of that coding style on the implementation.”

Now that Synopsys owns Synplicity’s toolset, are they the competition?

Shakeel said, “Actually, we complement the Synopsys flow quite well. At DATE this year in Grenoble, we announced an optimized flow with Synopsys, plus we’ve been exhibiting at the SNUG conferences. Next, we’ll be appearing at DesignCon 2013.”

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Given the confidence projected by the company and the aggressive conference schedule they are pursuing, expect to see a lot more from Blue Pearl, not just at DesignCon, but throughout the coming year and beyond.

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Tags: Altera, ARM TechCon, Blue Pearl, DATE, DesignCon, Grey Cell Methodology, RTL Signoff for FPGAs, SAME, Shakeel Jeeawoody, SNUG, Synopsys, Synplicity, Xilinx

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