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 What Would Joe Do?

Archive for December, 2012

GSS: a spirited defense of FDSOI

Thursday, December 13th, 2012

 

When it comes to stimulating, it doesn’t get better than stepping out of a session at IEDM in San Francisco to take a conference call from Glasgow. On Tuesday, December 11th, I stepped out of Session 9 and a presentation on spintronics to speak with Dr. Asen Asenov about a different device technology.

Asenov is a 20-year veteran of the University of Glasgow, where he serves as James Watt Professor of Electrical Engineering and heads up the Glasgow Device Modeling Group. He is also founder of Glasgow-based Gold Standard Simulations (GSS), a company that specializes in simulating statistical variability in nano-CMOS devices.

We spoke on December 11th because GSS announced that day the results of research “comparing the differentiation between metal gate first and metal gate last FDSOI [fully-depleted silicon-on-insulation] approaches, and comparing it to equivalent bulk MOSFETs.” Based on that work, the company announced that gate-last technology “offers significant advantages” over gate-first technology for devices built on 32- or 28-nanometer FDSOI, and noted that both nodes “significantly outpace equivalent bulk MOSFETS with respect to low-power SRAM design.”

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Blue Pearl: Facilitating FPGA design

Thursday, December 6th, 2012

 

Shakeel Jeeawoody is VP of marketing at Blue Pearl. I enjoyed a long conversation with Shakeel at SAME Forum in France in October, and again at ARM TechCon in November. We completed the discussion by phone this week, starting with a brief profile of Blue Pearl and a discussion of FPGA versus ASIC design needs.

Per Jeeawoody, “Blue Pearl has been around since 2005, we’re located in Santa Clara, and our technology has all been developed in-house. Our underlying technology improves RTL analysis using symbolic simulation techniques and adapting them to our customers’ market requirements. We have competitors in the linting and clock-domain crossing [CDC] space, but not many that can generate SDC constraints and offer easy-to-use tools that run on Windows at an attractive price point to support FPGA designers.

“More FPGA designers today struggle with IP integration in their projects in the same way ASIC designers have in the past; if they don’t do the right level of analysis, there are reliability problems in the field. With that in mind, we focus on addressing emerging and major FPGA design issues – one we call Grey Cell Methodology, and we offer mode-based analysis to address issues associated with longest path analysis.

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