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 What Would Joe Do?
Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

ProPlus: DFY solution unveiled

November 1st, 2012 by Peggy Aycinena

The leadership of ProPlus Design Solutions has a long history in EDA, although the company itself is a newly launched startup. Ten years ago, the majority of the leadership were involved in Celestry Design Technologies, Inc., while 5 years ago all of today’s ProPlus executive team were at Cadence. Today the company, based in Silicon Valley, is building on those many years of experience to make inroads in the demanding market for design-for-yield tools.

In late September, ProPlus released its newest product offering, NanoYield for yield prediction and design optimization. When I spoke with Dr. Zhihong Liu, Executive Chairman of the company, he touched on the history of ProPlus and explained the intent of NanoYield.

Per Liu, “ProPlus has foundation technology in modeling that goes back to Celestry, a company acquired by Cadence in 2003. When the team bought the technology out of Cadence, they founded ProPlus and [worked to create] a unique DFY solution, design for yield.

“Before I joined ProPlus two years ago, they were developing lines of technologies for both high-performance parallel modeling and circuit simulation/analysis with true SPICE accuracy. Now we have put everything together to provide an integrated solution for designing better circuits in shorter time, including modeling, simulation and multivariate statistical analysis. No one else in the industry is addressing all three of these together.

“One technology that was originally licensed from IBM is a multivariate High-Sigma solution. We put that together with our own industry-validated solution, and now provide the only integrated solution in the industry, NanoYield.”

Would the Big Three companies in EDA agree that they do not have comparable integrated solution?

Liu said, “I was at Cadence for almost 8 years, running the simulation, verification, and DFM divisions. Yet today at ProPlus, we understand all of these issues more than Cadence, more than Synopsys, and certainly more than Mentor. Overall, however, the closest solution to what we offer would be from Cadence.

“They have simulation technology, and they have Virtuoso XL, which has multivariate Monte Carlo analysis, but they don’t have CAD tools which were linked to the foundry in a constructive way as we do today. Cadence puts all of their resources into working with the foundries through PDKs. We, on the other hand, work with the foundries through our models.

“Today we work with leading foundries, for instance, addressing their statistical modeling solutions, viewing the model extraction flow and working at the device level to understand the impact of process variations.

“When I say we provide an integrated solution, here is what I mean: When you do multivariate analysis, you can use Monte Carlo analysis and get a 2x speed up. But when you do as we do – build the statistical analysis directly into the simulation – there’s a big advantage.

“We do much more than just integrate, however. [In our technology], each time you change a device parameter, you launch another simulation. Our solution today [removes the need] for huge compute farms, which is important because parallelization is not solving the problem.”

And what is the problem?

Per Liu: “Process variation is killing us, slowing down the proliferation of advanced technology. There are a lot of uncertainties around solving lot-to-lot, die-to-die, and wafer-to-wafer variations, all of which have been problems from the beginning of the semiconductor industry. But today, there is another set of issues – local random variations, which requires that we consider the problem statistically, requires the designers to design circuits in a statistical way.

“For instance, assuming two transistors in a circuit are identical is not correct. There is variation from actual device to device. The only way to deal with it accurately is to do a Monte Carlo analysis to look at statistical variations. In some cases, you need to do a high number of Monte Carlos – tens of millions of runs.

“Today, both Cadence and Synopsys are offering statistical analysis, but they are built on statistical timing engineering. But the infrastructure is largely not there. Instead they are trying to mimic the process using multi-space parallelization.

“There is another problem beyond statistical variation, however. People don’t know how to trust the yield from their foundry. The more aggressive the design, the lower the yield, which at advanced process technologies can be as low as 65-to-70 percent.”

At what node does deterministic variation in transistor devices drive the yield this low?

Liu said, “For all customers, the real question is: At what process technology will my design fall apart? For IBM, from 90 nanometers on they have been forcing their design tools to [deal with these variations].

“I think TSMC has data indicating that starting at 65 nanometers, the problems became more and more severe. Of course, TSMC would never say that there is a yield problem, but they would say that if you use models properly, your design will be more competitive when manufactured. Our models are the solution.”

Is there synergy between the ProPlus offerings and PDF Solutions?

Liu said, “Not very much. PDF has been there for a long time, but their major effort is around helping the foundries to communicate their yield to their customers. PDF helps the foundries identify the main factor in their unstable processes. We instead have been working with the foundries on their IP design, not their processes. We help them with the tradeoffs [that lead to] better designs.”

What are the specific tradeoffs the ProPlus tools look at?

Liu said, “First, there is the statistical variation information from the foundries. It is available to the designers, but they do not know how to use it properly.

“Second, there is the problem of how to use the models. A lot of designers don’t know how to use them, and yet do not have the time to run the simulations. People try to select just the most important part of the design and only run a few parts of the circuits in their simulations. That works for some designs, but more and more circuits are sensitive to variations, so the process [is inadequate].

“Finally, simulations need to be more powerful. The simulators from Cadence and Synopsys can run big circuits fast, but designers also want to run statistical analysis on both large and small circuits, plus in a simpler simulation environment, not bigger computer farms. Designers want a simulation that can be integrated into their design process. With our [technology] focusing on statistical analysis, they can run both large and small circuits, post layout, and do more with the variation.”

What do you say to engineers using your tools?

Liu said, “We tell the designers, the tools are for them, but their managers and CAD people will see our tools can improve efficiency as well. We also say, if you are one of the top 3 customers of TSMC you have many choices. If you do not have that kind of luxury, however, come talk with us. We have the judgment and the tools to help you.”


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