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Peggy Aycinena
Peggy Aycinena
Peggy Aycinena is a freelance journalist and Editor of EDA Confidential at She can be reached at peggy at aycinena dot com.

Verification update: Breker, EVE & SNPS, CDNS, Agilent & Aldec

July 12th, 2012 by Peggy Aycinena

It may be summertime, but the folks in the Verification world are clearly not taking any holidays.

This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!


Funding …

Breker Verification Systems announced $5 million in Series A funding from the Astor Capital Group, “a private equity fund out of Far East Asia.”

Per the Press Release: “Since its founding in 2003, Breker Verifications Systems’ mission has been to improve upon existing verification technologies, especially as multiple embedded processors become more and more prevalent in SoCs.”

The company says the Series A funds “will be used as working capital to scale Breker’s operations, expanding in all areas of sales, support and research and development.

“Previously, Breker bootstrapped the company with a small, initial round of angel investment. That funding enabled Breker to gain market traction with TrekSoC, the first commercially available software that automates the generation of self-verifying test cases for multi-threaded SoC devices. TrekSoC is in production use at leading SoC design companies, including STMicroelectronics and NVIDIA.”


Co-emulation methodology …

EVE announced that Ricoh is using EVE’s ZeBu hardware-assisted verification platform “to accelerate ASIC and SoC development.”

Per the Press Release: “ZeBu systems are being combined with Synopsys Virtualizer-based virtual prototypes to create a co-emulation environment that enables early embedded software development.

“To speed software development, Ricoh implemented a co-emulation methodology with the ability to combine existing RTL blocks with virtual models of the design, [and therefore] was able to compile the RTL for its design’s GPU into a ZeBu emulator and link with minimal effort to a Virtualizer-based virtual prototype containing system-level models of the CPU cores, buses and other logic. This approach saved the time and effort of creating models of pre-existing design blocks.”

Naoya Morita, Ricoh’s CH Development Center, Controller Development Division, is quoted: “We deployed the same environment for the development of GPU application software, as well as for OS boot development. On the OS boot development, we saw similar benefits as those we got in the GPU case.”


Verification IP …

Cadence announced new capabilities in its PCI Express Verification IP [PCIe VIP]:

* More in-depth verification of current PCIe specs at the block and SoC levels.
* New performance measurement utilities to optimize link utilization, throughput, latency, power.
* TripleCheck test suite, coverage model, verification plan integrated into single environment.
* PCIe VIP accelerated for 100x simulation throughput of UVM-complient testbenches with Palladium XP
* Support of latest PCIe specs: SR-IOV, MR-IOV, NVMe and PIPE4.

A. Vasudevan, VP at Wipro and Cadence customer, is quoted in the press release: “We have been consistently enabling semiconductor companies to reduce verification time and increase coverage parameters through next generation frameworks and market proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe 3.0 VIP, along with TripleCheck, to achieve a comprehensive solution that gives us the fastest path to IP verification closure.”


Co-simulation interface …

Aldec and Agilent Technologies announced a new co-simulation interface between Aldec’s Riviera-PRO design simulation and verification platform for FPGA, ASIC, and SoC development and Agilent’s SystemVue design and signal processing environment for physical layer design of wireless, RF and DSP applications.

Per the Press Release: “The new solution enables users to efficiently integrate algorithm and system-level designs with hardware implementations. The new co-simulation interface requires only one instance of Riviera-PRO (regardless of the number of HDL blocks on a SystemVue diagram), supports a range of data types, and provides extensive cross-domain debugging capabilities. This tight, bi-directional integration reduces development time and effort by enabling continuous test and system-level verification throughout the development process.”

Daren McClearnon, Agilent’s SystemVue Product Marketing Manager, is quoted: “Agilent system-level design products are now integrated into the hardware design flow, which enables system engineers to troubleshoot Verilog and VHDL hardware implementations, while still maintaining a higher-level view of PHY system performance.”

Dmitry Melnik, Aldec’s Riviera-PRO Product Manager, is also quoted: “Now engineers can re-use SystemVue components in hardware simulations while respective HDL blocks are being coded, or use SystemVue as a testbench to verify HDL implementation.”


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