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 What Would Joe Do?

Archive for July, 2012

Jim Hogan: Surf & Turf in Santa Cruz

Thursday, July 26th, 2012


There are three things to remember about Jim Hogan: He’s an affable guy, he’s usually sporting a Hawaiian shirt, and he’s extremely accessible; when you interview him, he’s able to talk to you without a PR person sitting at his elbow. I spoke with Jim by phone in late July.


WWJD: How are you doing, and what’s up with this upcoming surfing-themed fundraiser you’re hosting?

Jim Hogan: I’d doing great, and yeah – that’s an annual fund raiser we host. I live in Santa Cruz, where life is pretty easy and my kids surf.

Also I work a lot with Jill Jacobs [Mod Marketing], who’s got relatives here in Santa Cruz. Jill was my coordinator for roadshows at Cadence and still does logistics for some of my startups. Her relatives are just a great family and are neighbors with Jack O’Neal [surfing entrepreneur and credited by many for inventing the wetsuit] who’s always donating to charities here.

Santa Cruz isn’t too far from the Valley, and I always have a lot of fun when we put these two crowds together, the surfers and the technology folks. For me, it’s kind of like the parties we had at my frat in college. You pick the day, buy the beer, and invite a bunch of people. [laughing] Maybe we’ve scaled up a little bit since then. Now my frat parties have a somewhat corporate feel.


CDNS: What a difference a year [or 2] makes

Thursday, July 26th, 2012


We’re coming up on almost four years, full on, since the momentous events of 15 October 2008 when the entire top executive team at Cadence exited stage left.

At the time, of course, the world was paying a shade less attention to EDA, and a shade more attention to a global crisis unfolding minute-by-minute featuring household concepts such as bankruptcy, subprime mortgages, and derivatives, and household names such as Lehman Brothers, AIG, Merrill Lynch, Bank of America, Goldman Sachs, Morgan Stanley, Washington Mutual, JPMorgan, Wachovia, CitiGroup, and the FDIC, to name a few.

Meanwhile, the folks who held CDNS in mid-October 2008 were holding shares that had lost almost 80% of their value over the previous 12 months, plummeting from $20+/share to around $4/share in that time frame.

The world may have been consumed by news of the larger global meltdown in October 2008, but various CDNS shareholders were sufficiently focused on the disaster at Cadence to precipitate upwards of a dozen class-action suits against the company in protest.


EV update: LiPo battery, Tesla testimonial, Volt production, China mandate, Landlord veto

Tuesday, July 24th, 2012


As a follow-on to my June 21st blog regarding Electric Vehicles [EVs: an Electric Car in Every Garage], here are some additional notes of interest:

1 – An RC plane and car expert explained to me recently that if you want to follow the latest updates in battery technology, look to the RC marketplace. That market being full of avid hobbyists, it’s willing to embrace nascent technologies as early adopters.

The current technology that’s “hot” in RCs is the lithium polymer, or LiPo, battery. It’s still expensive, suffers from reduced shelf-life, and is reportedly more flammable than the lithium-ion battery technology currently installed in EVs, but the LiPo battery appears to offer “lighter weight and higher discharge rates” to power-hungry RC devices.

Per “In short, LiPo’s provide high energy storage to weight ratios in an endless variety of shapes and sizes.”

Thanks to the global RC user base, LiPo battery technology is enjoying intense research and deployment – not necessarily in that order – and may one day be widely utilized in the more “conventional” EV market. If the bugs can be worked out, the LiPo chemistry [possibly] stands to replace the “traditional” lithium-ion EV technology in years to come.


Accellera Systems Initiative: team effort & SystemC Library 2.3

Thursday, July 19th, 2012


This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn’t been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work.

I spoke by phone with Accellera Systems Initiative Language Working Group Chair David Black, Senior Member of Technical Staff at Doulos, on July 17th.

Black explained, “The purpose of Version 2.3 is to reflect the latest version of IEEE Standard 1666 – to fundamentally demonstrate new features introduced into the SystemC standard, which includes TLM 2.0, previously an OSCI-only standard and now part of the IEEE standard. Interested parties can download the SystemC 2.3 library from the Accellera Systems Initiative website. This download includes several bug fixes, the latest TLM 2.0 and new SystemC features”

I asked Black who has participated in this work, and how often they meet. He said, “The Language Working Group of Accellera Systems Initiative includes all of the major EDA vendors – Cadence, Mentor, Synopsys, and Forte – and service providers such as Doulos and Circuit Sutra – and various members of the industry such as Intel, TI and STMicro, with everyone contributing a perspective.

“I am the Co-Chair of the SystemC Language Working Group along with Andy Goodrich [Forte Design Systems] and took over my position from Mike Meredith [also with Forte]. Key contributors also include Tor Jeremiassen [TI], John Aynsley and Alan Fitch [Doulos], Bishnupriya Bhattacharya [Cadence],  Jerome Cornet [STMicroelectronics],  Dr. Torsten Maehne [UPMC], Pat Sheridan and Bart Vanthournout [Synopsys], and Philipp Hartmann [OFFIS], along with many others.


MathWorks: the elephant in the room

Wednesday, July 18th, 2012


To get to MathWorks’ corporate headquarters outside Boston, take the Red Line to the Orange Line to Back Bay Station. Take the Commuter Rail to Natick, cross the bridge over the tracks, walk north along leafy Walnut Street for a mile and a quarter, turn left onto Route 9, and cross the grass to Apple Hill Drive. Turn left into the parking lot of the company’s campus, pick your way through the construction going on there, and look for the main reception building across from the big parking structure.

If you do all of this, and it’s 90+ degrees with 60% humidity, you’ll be totally drenched by the time you walk into the cool of the MathWorks headquarters. But no worries; the very nice person at the reception desk will send you down the hall to the closest break room where you can get a tall drink from the beverage dispenser and bring it back to the reception area to rest, recuperate, and prepare for your meeting with Ken Karnofsky.

Okay, two points of interest here: a) MathWorks is different. It’s headquartered in a residential neighborhood, not a commercial park; and b) the welcome is relaxed and not the high-pressure stuff of Silicon Valley.

Two additional points of interest: c) MathWorks is expanding. They’ve got 2400 employees currently, with an additional 200 job openings! Their Natick campus may offer a calm retreat from a humid Massachusetts afternoon, but it’s not a calm retreat from the world because when you’re there, MathWorks feels to be at the center of the world.

And d) MathWorks is definitely an EDA company, even though they don’t belong to EDAC and they don’t exhibit at DAC (although they have exhibited in the past). If you design chips, MathWorks’ MATLAB and Simulink is the gateway into your design. When it comes to EDA, MathWorks is most definitely the elephant in the room.


MIT: towards the 1000-core processor

Tuesday, July 17th, 2012


MIT is a disorienting place, particularly Stata Center, the home of EECS. There are no straight lines in the building and nothing appears plumb. Architect Frank Gehry, it seems, wanted his design to disturb and overwhelm and there he has succeeded, particularly when it rains: The building leaks. But does the building also stimulate? Again, Gehry has succeeded: The building hums with energy.

On a sunny day in July, the place is crawling with people. Students of various ages, genders, and nationalities wander by chatting in their t-shirts and flip flops, professors share bag lunches with their children in shady corners of the labyrinthine lobby, the line at the deli counter queues around in a disorderly sort of meander, while people in suits mingle with the flip-flop crowd in and under staircases that wander up and off into brick-lined oblivion.

Stata is part intellectual Grand Central Station and part Winchester Mystery House, enticing tourists and visiting scholars alike to wander in off the ponderous corporate streets of Cambridge.

EECS Professor Srini Devadas has an office on the 8th floor of Stata. When we sat down to chat there on Monday, July 9th, he started with an enthusiastic endorsement of MIT’s most famous building.


Verification update: Breker, EVE & SNPS, CDNS, Agilent & Aldec

Thursday, July 12th, 2012


It may be summertime, but the folks in the Verification world are clearly not taking any holidays.

This week, four different verification-related news announcements arrived, presenting an interesting set of positive mid-year perspectives: Breker’s new round of funding, EVE and Synopsys’ co-emulation success, Cadence’s beefed-up PCIe VIP, and a new co-simulation interface from Aldec and Agilent. Good news on all fronts and now these folks should take a vacation!


EDA: 7 Grand Challenges

Wednesday, July 11th, 2012


The concept of a Grand Challenge is an established one in engineering, so here in 2012 what are the Grand Challenges in EDA? Let’s go out on a limb and name a few candidates:

No.1) Low power: This is the critical problem here in the era of mobile everything. If you can’t guarantee low power for your device, it’s going to go dark way too soon and be way too hot in the meanwhile. Great challenges remain in perfecting the tools to make this all happen.

No.2) Formal verification: There just has to be a way to guarantee that what we meant to design, has been designed and then manufactured. Isn’t that the goal of formal verification, and isn’t it true that we’re not quite there yet?

No.3) 3D-ICs: In the last several years, this one’s gotten a lot of attention, but it appears that there’s still a lot of work to do – at least on the logic side of the equation. Clearly more tools are needed.


BDA: Two different definitions at DAC

Tuesday, July 10th, 2012


It’s stranger than fiction, but there are actually two different entities at DAC that bear the name BDA, and they’re both acronyms.

One is a company very familiar to the EDA space, Berkeley Design Automation. As you know, President & CEO Ravi Subramanian has just been elected to a second term as a member of the Board of Directors of EDAC.

Subramanian’s BDA is in the news again this week because they just announced that ATopTech, also an EDA company, is now using BDA’s Analog FastSpice to “enhance the accuracy of the timing analysis in [ATopTech’s] Aprisa P&R product for designs at advanced process technology nodes such as 28nm and 20nm..”

So what is the other BDA at DAC? It’s Biological Design Automation. The International Workshop on Biological Design Automation figured large on Sunday and Monday, June 3rd and 4th, in San Francisco where it was again co-located with the Design Automation Conference, as it has been for several years.


SI: What comes after CDNS acquires Sigrity?

Thursday, July 5th, 2012


The SI landscape is a confusing one: What is the true value of a signal integrity analysis tool, and if you’re an EDA vendor, do you need to offer an in-house SI solution to be a true end-to-end provider?

Although Cadence has had a position in signal integrity with their OrCAD Signal Explorer [pre- and post-route topology exploration and transmission line analysis, conceptual, pre-design/schematic topology exploration and simulation, routed or unrouted board topology extraction and analysis] …

… this week Cadence announced it has acquired Silicon Valley-based Sigrity and will now incorporate Sigrity’s PowerSI [full-wave electrical analysis for IC packages and PCBs, identifies trace and via coupling, power/ground bounce, and design regions that are under or over voltage targets] and SystemSI [chip-to-chip signal integrity analysis, including parallel bus analysis and serial link analysis, frequency domain, time domain and statistical analysis] into Cadence’s flow.

This all sounds great as a strategy for beefing up Cadence’s SI offerings, but what does it do to Sigrity’s current set of partners: Apache [owned by Ansys], CST, Mentor Graphics, Synopsys’ HSPICE, TSMC, and Zuken?


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